IS41C44052C データシートの表示（PDF） - Integrated Silicon Solution
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IS41C44052C Datasheet PDF : 17 Pages
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IS41C44052C
IS41LV44052C
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50 -60
Symbol Parameter
Min. Max.
Min. Max.
trwl
Write Command to RAS Lead Time(17)
13
—
15
—
tcwl
Write Command to CAS Lead Time(17, 21)
8
—
10
—
twcs
tdhr
Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
0
—
39
—
0
—
39
—
tach
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
toeh
OE Hold Time from WE during
READ-MODIFY-WRITE cycle(18)
15
—
8
—
15
—
10
—
tds
Data-In Setup Time(15, 22)
0
—
0
—
tdh
Data-In Hold Time(15, 22)
8
—
10
—
trwc
trwd
tcwd
tawd
READ-MODIFY-WRITE Cycle Time
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
108
—
64
—
26
—
39
—
133
—
77
—
32
—
47
—
tpc
trasp
tcpa
Fast Page Mode READ or WRITE
Cycle Time
RAS Pulse Width
Access Time from CAS Precharge(15)
20
—
50
100K
—
30
25
—
60
100K
—
35
tprwc
tcoh
READ-WRITE Cycle Time(24)
Data Output Hold after CAS LOW
56
—
5
—
68
—
5
—
toff
twhz
tcsr
tchr
tord
Output Buffer Turn-Off Delay from
CAS or RAS(13,15,19, 24)
Output Disable Delay from WE
CAS Setup Time (CBR REFRESH)(20, 25)
CAS Hold Time (CBR REFRESH)( 21, 25)
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
0
12
3
10
5
—
8
—
0
—
0
15
3
10
5
—
10
—
0
—
tref
Auto Refresh Period 2,048 Cycles
—
32
—
32
tt
Transition Time (Rise or Fall)(2, 3)
1
50
1
50
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
AC TEST CONDITIONS
Output load: Two TTL Loads and 50 pF (Vdd = 5.0V ±10%)
One TTL Load and 50 pF (Vdd = 3.3V ±10%)
Input timing reference levels: Vih = 2.0V, Vil = 0.8V (Vdd = 5.0V ±10%);
Vih = 2.0V, Vil = 0.8V (Vdd = 3.3V ±10%)
Output timing reference levels: Voh = 2.4V, Vol = 0.4V (Vdd = 5V ±10%, 3.3V ±10%)
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. 00B
08/09/2010
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