LH5496D-65 データシートの表示（PDF） - Sharp Electronics

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LH5496D-65

CMOS 512 × 9 FIFO

Sharp Electronics 

LH5496/96H

TIMING DIAGRAMS (cont’d)

W

tWEF

EF

R

NOTES:

1. tRPE = tRPW

2. tRPE: Effective Read Pulse Width after Empty Flag HIGH.

3. The Data Out pins (D0 - D8) are forced into a

high-impedance state whenever EF = LOW.

Figure 11. Empty Flag Timing

CMOS 512 × 9 FIFO

tRPE

5496-10

R

tRFF

FF

tWPF

W

NOTES:

1. tWPF = tWPW

2. tWPF: Effective Write Pulse Width after Full Flag HIGH.

Figure 12. Full Flag Timing

5496-11

HALF-FULL

OR LESS

W

R

HF

MORE THAN

HALF-FULL

t WHF

10

HALF-FULL

OR LESS

tRHF

5496-12

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