LH5496U-50 データシートの表示（PDF） - Sharp Electronics
部品番号
コンポーネント説明
メーカー
LH5496U-50 Datasheet PDF : 16 Pages
| |||
CMOS 512 × 9 FIFO
TIMING DIAGRAMS (cont’d)
LH5496/96H
D0 - D8
W
R
VALID DATA IN
tRPE
EF
t WEF
t WLZ
tREF
tA
Q0 - Q8
NOTES:
1. tRPE = tRPW
2. tRPE: Effective Read Pulse Width after Empty Flag HIGH.
3. The Data Out pins (D0 - D8) are forced into a
high-impedance state whenever EF = LOW.
VALID DATA OUT
Figure 9. Read Data Flow-Through
5496-8
R
tWPF
W
t RFF
FF
t WFF
D0 - D8
tA
Q0 - Q8
VALID DATA OUT
NOTES:
1. tWPF = tWPW
2. tWPF: Effective Write Pulse Width after Full Flag HIGH.
Figure 10. Write Data Flow-Through
t DS
t DH
VALID DATA IN
5496-9
9
Share Link: 