Q67006-A9225-C703(2000) データシートの表示（PDF） - Infineon Technologies

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Q67006-A9225-C703
(Rev.:2000)

5-V Low-Drop Fixed Voltage Regulator

Infineon Technologies 

TLE 4279

Circuit Description

The control amplifier compares a reference voltage, made highly accurate by resistance

balancing, with a voltage proportional to the output voltage and drives the base of the

series PNP transistor via a buffer. Saturation control as a function of the load current

prevents any over-saturation of the power element.

The reset output RO is in high-state if the voltage on the delay capacitor CD is greater or

equal VUD. The delay capacitor CD is charged with the current ID for output voltages

greater than the reset threshold VRT. If the output voltage gets lower than VRT (’reset

condition’) a fast discharge of the delay capacitor CD sets in and as soon as VD gets lower

than VLD the reset output RO is set to low-level.

The time gap for the delay capacitor discharge is the reset reaction time tRR.

The reset threshold VRT can be decreased via an external voltage divider connected to

the pin RADJ. In this case the reset condition is reached if VQ < VRT and VRADJ < VRAQDJ, TH.

Dimensioning the voltage divider (see Figure 4) according to

VTHRES = VRADJ,TH × R( RADJ1 + R ) RADJ2 / R , RADJ2

the reset threshold can be decreased down to 3.5 V. If the reset-adjust-option is not

needed the RADJ-pin should be connected to GND causing the reset threshold to go to

its default value (typ. 4.65 V).

A built in comparator compares the signal of the pin SI, normally fed by a voltage divider

from the input voltage, with the reference and gives an early warning on the pin SO. It is

also possible to superwise another voltage e.g. of a second regulator, or to build a

watchdog circuit with few external components.

Application Description

The input capacitor CI is necessary for compensating line influences. Using a resistor of

approx. 1 Ω in series with CI, the oscillating circuit consisting of input inductivity and input

capacitance can be damped. The output capacitor CQ is necessary for the stability of the

regulating circuit. Stability is guaranteed at values ≥ 10 µF and an ESR ≤ 10 Ω within the

operating temperature range. Both reset output and sense output are open collector

outputs and have to be connected to 5 V output via external pull-up resistors ≥ 10 kΩ.

For small tolerances of the reset delay the spread of the capacitance of the delay

capacitor and its temperature coefficient should be noted.

Data Sheet Rev. 2.3

4

2000-09-27

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