ISL36111DRZ-TS データシートの表示（PDF） - Renesas Electronics
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ISL36111DRZ-TS Datasheet PDF : 9 Pages
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ISL36111
Application Information
Typical application schematic for ISL36111 is shown in Figure 8.
DT
INPUT SIGNAL
LOSB (output)
100nF
100nF
1.2V
1
VDD
2
IN_P
3
IN_N
4
LOSB
ISL36111
1.2V
VDD 12
OUT_P 11
OUT_N 10
VDD 9
1.2V
100nF
100nF
OUTPUT SIGNAL
47nF
100pF
CPA
CPB
NOTES:
14. See “Control Pin Boost Setting” on page 5 for information on how to connect the CP pins
15. See “Detection Thereshold (DT) Pin Functionality” on page 6 for details on DT pin operation.
16. Although the filtering network is shown only for one VDD pin for simplicity, all the VDD pins need to be connected in this way.
FIGURE 8. TYPICAL APPLICATION REFERENCE SCHEMATIC FOR ISL36111
PCB Layout Considerations
Because of the high speed of the ISL36111 signals, careful PCB
layout is critical to maximize performance. The following
guidelines should be adhered to as closely as possible:
• All high speed differential pair traces should have a
characteristic impedance of 50 with respect to ground plane
and 100 with respect to each other.
• Avoid using vias for high speed traces as this will create
discontinuity in the traces characteristic impedance.
• Input and output traces need to have DC blocking capacitors
(100nF). Capacitors should be placed as close to the chip as
possible.
• For each differential pair, the positive trace and the negative
trace need to be of same length in order to avoid intra-pair
skew. Serpentine technique may be used to match trace
lengths.
• Maintain a constant solid ground plane underneath the high-
speed differential traces
• Each VDD pin should be connected to 1.2V and also bypassed
to ground through a 47nF and a 100pF capacitor in parallel.
Minimize the trace length and avoid vias between the VDD pin
and the bypass capacitors in order to maximize the power
supply noise rejection.
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FN6974 Rev 2.00
Jul 12, 2012
Page 7 of 9
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