ISL6550C データシートの表示（PDF） - Intersil
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ISL6550C Datasheet PDF : 11 Pages
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ISL6550A, ISL6550B, ISL6550C
Electrical Specifications TA = 25oC, and VDD = 12V, unless otherwise specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE AMPLIFIER
Input Offset Voltage
All Conditions
-
-
3.0
mV
Input Bias Current
All Conditions
-
-
200
nA
Input Offset Current
All Conditions
-
20
50
nA
Open Loop Gain
All Conditions
85
-
-
dB
Common-Mode Rejection Ratio
Vin ranges from 0V to 6V
80
-
-
dB
Power Supply Rejection Ratio
1mA Load
90
-
-
dB
Output
2mA source or 0.2mA sink
0.15
-
5
V
Maximum output current source
All
-2
-7
-
mA
Maximum output current sink
All
0.2
4
-
mA
Slew Rate
All
4
-
-
v/µS
Phase Margin
100pF load Condition
-
45
-
deg
Input Common Mode Voltage
0
-
6
V
Gain-Bandwidth Product
All
7.4
-
-
MHz
MONITOR CIRCUITRY
Input Common Mode Range
OV, UV Comparators
0
-
6
V
Propagation Delay
OV, UV Comparators
-
-
1.0
µS
PGOOD, START Outputs
PGOOD Voltage Low
IPGOOD = 5.0mA
-
0.27
0.4
V
START Voltage Low
ISTART = 5.0mA
-
0.21
0.4
V
Transistor Breakdown Voltage
All Conditions
15
-
-
V
Transistor Leakage
All Conditions
-
-
5
µA
PEN
Input LPUL (Vih)
2
-
-
V
Input MPDL (Vil)
-
-
0.8
V
Input Pull-Up Current
PEN = 0V
-15
-10
-
µA
Input Leakage Current
PEN = 5V
-
-
1
µA
OV/UV
UV and OV Threshold Hysteresis
% of (Vbdac-Vovuvth); logic option B
-
40
-
%
UV and OV Threshold Hysteresis
% of (Vbdac-Vovuvth); logic options A, C
-
10
-
%
NOTES:
3. The total resistance of R1 + R2 + R3 of 50kΩ is preferred to minimize error due to DACHI and DACLO input currents. Choose the values within
this limitation such that the voltages at DACHI and DACLO are those desired for the high and low limits of the programming range. For example,
Choosing R1 and R2 to be 15K and R3 to be 20K will produce a DAC range of 2.0V to 3.5V.
4. DAC Output Error as defined here assumes that the voltages applied to DACHI and DACLO are exact. The limits include errors introduced by
source impedance up to 12.5K and DACHI and DACLO. The error in Vdachi and Vdaclo (i.e. VREF5 error + external resistor divider error) must
be included to arrive at the total BDAC output error.
6
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