ICX432DQ データシートの表示（PDF） - Sony Semiconductor
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ICX432DQ
Sony Semiconductor
ICX432DQ Datasheet PDF : 30 Pages
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ICX432DQ
Bias Conditions
Item
Symbol
Min.
Typ.
Max.
Unit Remarks
Supply voltage
VDD
14.55
15.0
15.45
V
Protective transistor bias
VL
∗1
Substrate clock
φSUB
∗2
Reset gate clock
φRG
∗2
∗1 VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply for
the V driver should be used.
∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Supply current
Symbol
Min.
Typ.
Max.
Unit Remarks
IDD
5.0
7.0
9.0
mA
Clock Voltage Conditions
Item
Symbol
Min.
Readout clock voltage VVT
14.55
VVH1, VVH2
VVH3, VVH4
–0.05
VVH5, VVH6
–0.2
VVL1, VVL2,
VVL3, VVL4,
VVL5, VVL6
–8.0
Vertical transfer clock
voltage
VφV
VVH5 – VVH
6.8
–0.25
VVH6 – VVH
–0.25
VVHH
VVHL
VVLH
VVLL
VφH
Horizontal transfer
clock voltage
VHL
VCR
3.0
–0.05
0.5
Reset gate clock
voltage
VφRG
3.0
VRGLH – VRGLL
VRGL – VRGLm
Substrate clock voltage VφSUB
21.5
Typ.
15.0
0
0
–7.5
7.5
3.3
0
1.65
3.3
22.5
Max.
Unit
Waveform
Diagram
Remarks
15.45 V
1
0.05 V
2
VVH = (VVH1 + VVH2 + VVH3
+ VVH4)/2
0.05 V
2
–7.0 V
2
VVL = (VVL5 + VVL6)/2
8.05 V
0.1 V
0.1 V
0.8 V
0.9 V
0.9 V
0.8 V
3.6 V
0.05 V
V
3.6 V
0.4 V
0.5 V
23.5 V
2
VφV = VVHn – VVLn (n = 1 to 6)
2
2
2 High-level coupling
2 High-level coupling
2 Low-level coupling
2 Low-level coupling
3
3
3 Cross-point voltage
4
4 Low-level coupling
4 Low-level coupling
5
–4–
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