WED3EG6417S-D4 データシートの表示（PDF） - White Electronic Designs Corporation

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WED3EG6417S-D4

128MB - 16Mx64 DDR SDRAM UNBUFFERED

White Electronic Designs Corporation 

White Electronic Designs

WED3EG6417S-D4

*ADVANCED

DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A

IDD1 : OPERATING CURRENT: ONE

BANK

1. Typical Case : VCC = 2.5V, T = 25°C

2. Worst Case : VCC = 2.7V, T = 10°C

3. Only one bank is accessed with tRC (min), Burst

Mode, Address and Control inputs on NOP edge are

changing once per clock cycle.

Iout = 0mA

4. Timing patterns

-DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL = 4,

tRCD = 2*tCK, tRAG = 5*tCK

Read : A0 N R0 N N P0 N A0 N - repeat the same

timing with random address changing; 50% of data

changing at every burst

-DDR266B (133MHz, CL = 2.5): tCK = 7.5ns, CL = 2.5,

BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAG = 5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the

same timing with random address changing; 50% of

data changing at every burst

-DDR266A (133MHz, CL = 2) : tCK = 7.5ns, CL = 2, BL

= 4, tRCD = 3*tCK, tRC = 9*tCK, tRAG = 5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the

same timing with random address changing; 50% of

data changing at every burst

IDD7A : OPERATING CURRENT : FOUR

BANK OPERATION

1. Typical Case : VCC = 2.5V, T = 25°C

2. Worst Case : VCC = 2.7V, T = 10°C

3. Four banks are being interleaved with tRC (min), Burst

Mode, Address and Control inputs on NOP edge are

not changing.

Iout = 0mA

4. Timing patterns

-DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL =

4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 -

repeat the same timing with random address

changing; 100% of data changing at every burst

-DDR266B (133MHz, CL = 2.5) : tCK = 7.5ns, CL =

2.5, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK

Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1

R0 - repeat the same timing with random address

changing; 100% of data changing at every burst

-DDR266A (133MHz, CL = 2) : tCK = 7.5ns, CL2 = 2,

BL = 4, tRRD = 2*tCK, tRCD = 3*tCK

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1

R0 - repeat the same timing with random address

changing; 100% of data changing at every burst

Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP,

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

March 2002

Rev. # 0

6

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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