MICRF001BM データシートの表示（PDF） - Micrel

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MICRF001BM

QwikRadio Receiver/Data Demodulator

Micrel 

MICRF001

QwikRadio tm

Ordering Information

Part Number

MICRF001BN

MICRF001BM

Temperature Range

-40°C to +85°C

-40°C to +85°C

Package

14-Pin DIP

14-Pin SOIC

Pin Configuration (DIP and SOIC)

Micrel

Pin Description

Figure 1

Pin Number

1

2/3

4

5

6

7

8

9/10

11

12

13

14

Pin Name

SEL0

VSSRF

ANT

VDDRF

VDDBB

CTH

DO

VSSBB

CAGC

SEL1

REFOSC

SWEN

Pin Function

Programs desired Demodulator Filter Bandwidth. This pin in internally pulled-up to VDD. See Table 1.

This pin is the ground return for the RF section of the IC. The bypass capacitor connected from VDDRF to

VSSRF should have the shortest possible lead length. For best performance, connect VSSRF to VSSBB at

the power supply only (i.e., keep VSSBB currents from flowing through VSSRF return path).

This is the receive RF input, internally ac-coupled. Connect this pin to the receive antenna. Input

impedance is high (FET gate) with approximately 2pF of shunt (parasitic) capacitance. For applications

located in high ambient noise environments, a fixed value band-pass network may be connected between

the ANT pin and VSSRF to provide additional receive selectivity and input overload protection. (See

“Application Note 22, MICRF001 Theory of Operation”.)

This pin is the positive supply input for the RF section of the IC. VDDBB and VDDRF should be connected

directly at the IC pins. Connect a low ESL, low ESR decoupling capacitor from this pin to VSSRF, as short

as possible.

This pin is the positive supply input for the baseband section of the IC. VDDBB and VDDRF should be

connected directly at the IC pins.

This capacitor extracts the (DC) average value from the demodulated waveform, which becomes the

reference for the internal data slicing comparator. Treat this as a low-pass RC filter with source impedance

described in Table 1 . (See “Application Note 22, MICRF001 Theory of Operation”, section 6.4). A

standard ± 20% X7R ceramic capacitor is generally sufficient.

Output data pin. CMOS level compatible.

This is the ground return for the baseband section of the IC. The bypass and output capacitors connected

to VSSBB should have the shortest possible lead lengths. For best performance, connect VSSRF to

VSSBB at the power supply only (i.e., keep VSSBB currents from flowing through VSSRF return path).

Integrating capacitor for on-chip receive AGC. The Decay/Attack time-constant (TC) ratio is nominally set

as 10:1. CAGC = 10(Attack Time Constant) µF. A standard ± 20% X7R ceramic capacitor is generally

sufficient.

Programs desired Demodulator Filter Bandwidth. This pin in internally pulled-up to VDD. See Table 1.

This is the timing reference for on-chip tuning and alignment. Either connect a ceramic resonator between

this pin and VSSBB, or drive the input with an AC coupled 0.5Vpp input clock. Use ceramic resonators

without integral capacitors. See “Application Note 22, MICRF001 Theory of Operation” for details on

frequency selection and accuracy.

This logic pin controls the operating mode of the MICRF001. When SWEN = HIGH, the MICRF001 is in

SWP mode. This is the normal (default) mode of the device. When SWEN = LOW, the device operates as

a conventional single-conversion superheterodyne receiver. (See “Application Note 22, MICRF001 Theory

of Operation” for details.) This pin is internally pulled-up to VDD.

June 1998

2

MICRF001

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