CXL5505M データシートの表示（PDF） - Sony Semiconductor

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CXL5505M

CMOS-CCD 1H Delay Line for PAL

Sony Semiconductor 

CXL5505M/P

(4) In figure below, differential gain (DG) and differential phase (DP) are tested with a vector scope when

the 5-staircase wave is fed.

150mV

350mV

500mV

150mV

1H 64µs

Input waveform

(5) The internal clock component to the output signal during no-signal input and the leakage of that high

harmonic component are tested.

Test value

(mVp-p)

(6) S/N ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in

BPF 100kHz to 5MHz, Sub Carrier Trap mode.

Clock

175mV

325mV

150mV

1H 64µs

Input waveform

fsc (4.433619MHz) sine wave

0.3 to 1.0Vp-p

(0.5Vp-p typ.)

–4–

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