PDM31256SA10TA データシートの表示（PDF） - Paradigm Technology
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PDM31256SA10TA Datasheet PDF : 7 Pages
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Write Cycle No. 1 (Write Enable Controlled)
t WC
ADDR
t AW
t CW
t AH
CE
t AS
WE
t WP
DIN
DOUT
t HZWE
t DS
t DH
DATA VALID
HIGH Z
t LZWE
PDM31256
Write Cycle No. 2 (Chip Enable Controlled)
ADDR
CE
t WC
t AW
tAS
tCW
t AH
t WP
WE
t DS
t DH
DIN
DATA VALID
UNDEFINED
DON'T CARE
AC Electrical Characteristics
Description
-10
-12
-15
-17
-20
WRITE Cycle
Sym Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
WRITE cycle time
Chip enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
Write pulse width
Data setup time
Data hold time
Write disable to output in low Z(4,5)
Write enable to output in high Z(4,5)
tWC 10
12
15
17
20
ns
tCW 10
10
12
12
13
ns
tAW 10
10
12
12
13
ns
tAS
0
0
0
0
0
ns
tAH
0
0
0
0
0
ns
tWP
8
10
11
11
12
ns
tDS
7
7
7
8
9
ns
tDH
0
0
0
0
0
ns
tLZWE 0
0
0
0
0
ns
tHZWE
3
3
3
3
3 ns
6
Rev. 3.3 - 4/29/98
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