MC145220DT データシートの表示（PDF） - Freescale Semiconductor

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MC145220DT

Dual 1.1 GHz PLL Frequency Synthsizer

Freescale Semiconductor 

Freescale Semiconductor, Inc.

ANALOG CHARACTERISTICS — CURRENT SOURCE/SINK OUTPUTS — PDout/φR AND PDout′/φR′

(Phase/Frequency Detectors Configured with PDout Outputs, Iout ≤ 2 mA @V+ = V+i = 4.5 to 5.5 V, Iout ≤ 1 mA @V+ = V+i = 2.7 to 4.4 V,

GND = GNDi, Voltages Referenced to GND)

Parameter

Test Condition

Guaranteed

Limit

Unit

Maximum Source Current Variation Part–to–Part (Notes 3 and 4) Vout = 0.5 x V+

± 20

%

Maximum Sink–versus–Source Mismatch

(Note 3) Vout = 0.5 x V+

12

%

Output Voltage Range

(Note 3) Iout variation ≤ 20%

0.5 to V+ – 0.5 V

V

NOTES:

1. Percentages calculated using the following formula: (Maximum Value – Minimum Value)/Maximum Value.

2. See Rx Pin Description for external resistor values.

3. This parameter is guaranteed for a given temperature within – 40 to 85°C and given supply voltage within 2.7 to 5.5 V.

4. Applicable for the Rx/φV or Rx′/φV′ reference pin tied to the GND or GND′ pin through a resistor. See Pin Descriptions for suggested resistor

values.

AC INTERFACE CHARACTERISTICS

(V+ = V+i = 2.7 to 5.5 V, GND = GNDi, TA = – 40 to 85°C, CL = 25 pF, Input tr = tf = 10 ns)

Symbol

fclk

tPLH, tPHL

tPZL, tPLZ

tTLH, tTHL

Cin

Parameter

Serial Data CLK Frequency

NOTE: Refer to Clock tw below

Maximum Propagation Delay, CLK to Output A (Selected as Data Out)

(Figure 1)

(Figures 1 and 5)

Maximum Propagation Delay, ENB to Output A (Selected as Port)

(Figures 2 and 6)

Maximum Output Transition Time, Output A; tTHLonly, on Output A when Selected as Port

(Figures 1, 5, and 6)

Maximum Input Capacitance — Din, CLK, ENB

Guaranteed

Limit

dc to 2.0

200

200

200

10

Unit

MHz

ns

ns

ns

pF

TIMING REQUIREMENTS (V+ = V+i = 2.7 to 5.5 V, GND = GNDi, TA = – 40 to 85°C, Input tr = tf = 10 ns unless otherwise indicated)

Symbol

Parameter

Guaranteed

Limit

Unit

tsu, th

Minimum Setup and Hold Times, Din versus CLK

(Figure 3)

50

ns

tsu, th, trec Minimum Setup, Hold, and Recovery Times, ENB versus CLK

(Figure 4)

100

ns

tw

Minimum Pulse Width, ENB

(Figure 4)

*

cycles

tw

Minimum Pulse Width, CLK

(Figure 1)

250

ns

tr, tf

Maximum Input Rise and Fall Times — CLK

(Figure 1)

100

µs

* The minimum limit is 3 REFin cycles or 195 fin or fin′ cycles with selection of a 64/65 prescale ratio or 99 fin or fin′ cycles with selection of a 32/33

prescale ratio, whichever is greater.

MC145220

4

MOTOROLA WIRELESS SEMICONDUCTOR

For More Information On This Product, SOLUTIONS DEVICE DATA

Go to: www.freescale.com

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