MAX9452 データシートの表示（PDF） - Microsemi Corporation
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MAX9452 Datasheet PDF : 19 Pages
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High-Precision Clock Generators
with Integrated VCXO
Pin Description
PIN
1
2, 3
4, 5
6, 25
7, 8
9
10
11
12
13
14, 15
16
17
18, 24
NAME
LOCK
FUNCTION
Lock Indicator. LOCK goes low when the PLL locks. LOCK is high when the PLL is not locked.
SEL0, SEL1
INO_ and IN1_ Select Inputs. Drive SEL0 high to activate IN0; drive SEL1 high to activate IN1. Driving SEL0
and SEL1 low disables the corresponding input. A 165kΩ pullup resistor pulls SEL0 and SEL1 up to VDD.
IN0+, IN0- Differential Reference Input Pair. IN0+ and IN0- accept LVPECL, LVDS, and LVCMOS signals.
VDD
Digital Power Supply. Connect a 2.4V to 3.6V power supply to VDD. Bypass VDD to GND with a 0.1µF
capacitor.
IN1+, IN1- Differential Reference Input Pair. IN1+ and IN1- accept LVPECL, LVDS, and LVCMOS signals.
INT Reference Input Condition Indicator. A high indicates a failed reference.
MR
Master Reset. Drive MR high to reset all I2C registers to their default state and INT to zero.
GND/CS
SCL
SDA
Ground and Chip-Select Input. Connect to GND in I2C mode. This is the chip-select input in SPI mode.
Clock Input. SCL is the clock input in I2C bus mode and SPI bus mode.
Data Input. SDA is the data input in I2C bus mode and SPI bus mode.
AD0, AD1
I2C Address Selection. Drive AD0 and AD1 high to convert the serial interface from I2C to SPI. GND/CS
becomes CS. See Table 3 for the unique addresses list.
CMON Clock Monitor. Drive CMON low to enable the clock monitor. Drive CMON high to disable the clock monitor.
OE
Output Enable Input. Drive OE low to enable the clock outputs. Driving OE high disables the clock outputs,
and the outputs go high impedance. An internal 165kΩ pullup resistor pulls OE up to VDD.
VDDQ
Clock-Output Power Supply. Connect a 2.4V to 3.6V power supply to VDDQ for the MAX9450 and MAX9452.
Connect a 1.5V power supply to VDDQ for the MAX9451. Connect a 0.1µF bypass capacitor from VDDQ to
GND.
19, 20
21
22, 23
26, 27
28
29, 30
31
32
EP
CLK0-,
CLK0+
GND
CLK1-,
CLK1+
X1, X2
VDDA
LP1, LP2
GNDA
RJ
EP
Differential Clock Output 0. The MAX9450 features LVPECL outputs. The MAX9451 features HSTL outputs
and the MAX9452 features LVDS outputs.
Digital GND
Differential Clock Output 1. The MAX9450 features LVPECL outputs. The MAX9451 features HSTL outputs,
and the MAX9452 features LVDS outputs.
Reference Crystal Input. Connect the reference crystal from X1 to X2.
Analog Power Supply. Connect a 2.4V to 3.6V power supply to VDDA. Bypass VDDA to GNDA with a 0.1µF
capacitor.
External Loop Filter. Connect an RC circuit between LP1 and LP2. See the External Loop Filter section.
Analog Ground
Charge-Pump Set Current. Connect an external resistor to GND to set the charge-pump current. See
Table 11.
Exposed Paddle. Connect to ground.
6 _______________________________________________________________________________________
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