MAX3673 データシートの表示（PDF） - Microsemi Corporation
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MAX3673 Datasheet PDF : 17 Pages
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19-44; Rev 0; 2/09
EVALUATION KIT AVAILABLE
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
General Description
The MAX3673 is a low-jitter frequency synthesizer that
accepts two reference clock inputs and generates nine
phase-aligned outputs. The device features 40kHz jitter
transfer bandwidth, 0.3psRMS (12kHz to 20MHz) inte-
grated phase jitter, and best-in-class power-supply
noise rejection (PSNR), making it ideal for jitter clean-
up, frequency translation, and clock distribution in wire-
less base-station applications.
The MAX3673 operates from a single +3.3V supply and
typically consumes 400mW. The IC is available in an
8mm x 8mm, 56-pin TQFN package, and operates from
-40°C to +85°C.
Applications
3G Wireless Base Stations
Frequency Translation
Jitter Cleanup
Clock Distribution
Pin Configuration and Typical Application Circuits appear at
end of data sheet.
Features
♦ Two Reference Clock Inputs: LVPECL
♦ Nine Phase-Aligned Clock Outputs: LVPECL
♦ Input Frequencies: 61.44MHz,122.88MHz,
245.76MHz, 307.2MHz
♦ Output Frequencies: 61.44MHz, 122.88MHz,
153.6MHz, 245.76MHz, 307.2MHz
♦ Low-Jitter Generation: 0.3psRMS (12kHz to 20MHz)
♦ Clock Failure Indicator for Both Reference Clocks
♦ External Feedback Provides Zero-Delay Capability
♦ Low Output Skew: 20ps Typical
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX3673ETN+
-40°C to +85°C
56 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Functional Diagram
REFCLK0
REFCLK0
REFCLK1
REFCLK1
IN0FAIL
IN1FAIL
LOCK
MR
SEL_CLK
DM
CPLL
0.1μF
0
DIV M
PFD
1
61.44MHz
CREG
0.22μF
DA
PLL_BYPASS OUTA_EN
1
CP
VCO
DIV A
0
2.457GHz
SIGNAL QUALIFIER
AND
LOCK DETECT
POWER-ON
RESET
(POR)
DIV N
1
DIV B
0
MAX3673
1
0
OUTA3
OUTA3
OUTA2
OUTA2
OUTA1
OUTA1
OUTA0
OUTA0
OUTB_EN
OUTB4
OUTB4
OUTB3
OUTB3
OUTB2
OUTB2
OUTB1
OUTB1
OUTB0
OUTB0
FB_SEL FB_IN FB_IN
DB
1
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