ISPLSI1016E-100LJNI データシートの表示（PDF） - Lattice Semiconductor

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ISPLSI1016E-100LJNI

In-System Programmable High Density PLD

Lattice Semiconductor 

Functional Block Diagram

Figure 1. ispLSI 1016E Functional Block Diagram

Specifications ispLSI 1016E

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

Generic

Logic Blocks

(GLBs)

A0

A1

A2

Global

B7

B6

B5

B4

S GOE 0/IN 3

MODE/IN 2

N I/O 31

IG I/O 30

I/O 29

I/O 28

SI/O 27

EI/O 26

I/O 25

D I/O 24

I/O 7

A3

I/O 8

A4

I/O 9

I/O 10

I/O 11

A5

I/O 12

A6

I/O 13

I/O 14

I/O 15

A7

SDI/IN 0

SDO/IN 1

Routing

Pool

(GRP)

B3

WB2

NEB1

FOR

B0

Clock

Distribution

CLK 0

CLK 1

CLK 2

I/O 23

I/O 22

I/O 21

I/O 20

I/O 19

I/O 18

I/O 17

I/O 16

A ispEN

Megablock

6E *Note: Y1 and RESET are multiplexed on the same pin

Network

IOCLK 0

IOCLK 1

0139B(1a)-isp

101 The device also has 32 I/O cells, each of which is directly

I connected to an I/O pin. Each I/O cell can be individually

S programmed to be a combinatorial input, registered in-

L put, latched input, output or bi-directional

I/O pin with 3-state control. The signal levels are TTL

p compatible voltages and the output drivers can source

is 4 mA or sink 8 mA. Each output can be programmed

independently for fast or slow output slew rate to mini-

mize overall output switching noise.

SE Eight GLBs, 16 I/O cells, two dedicated inputs and one

ORP are connected together to make a Megablock (see

UFigure 1). The outputs of the eight GLBs are connected

to a set of 16 universal I/O cells by the ORP. Each ispLSI

1016E device contains two Megablocks.

The GRP has, as its inputs, the outputs from all of the

GLBs and all of the inputs from the bi-directional I/O cells.

All of these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI 1016E device are selected using the

Clock Distribution Network. Three dedicated clock pins

(Y0, Y1 and Y2) are brought into the distribution network,

and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0

and IOCLK 1) are provided to route clocks to the GLBs

and I/O cells. The Clock Distribution Network can also be

driven from a special clock GLB (B0 on the ispLSI 1016E

device). The logic of this GLB allows the user to create an

internal clock from a combination of internal signals

within the device.

2

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