ISPLSI1016E-100LJNI データシートの表示（PDF） - Lattice Semiconductor

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ISPLSI1016E-100LJNI

In-System Programmable High Density PLD

Lattice Semiconductor 

Specifications ispLSI 1016E

Internal Timing Parameters1

PARAMETER #2

DESCRIPTION

-125

-100

-80

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.

Outputs

tob

49 Output Buffer Delay

– 1.4 – 1.7 – 3.0 ns

tsl

toen

todis

tgoe

Clocks

tgy0

tgy1/2

tgcp

50 Output Slew Limited Delay Adder

51 I/O Cell OE to Output Enabled

52 I/O Cell OE to Output Disabled

53 Global Output Enable

54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

55 Clock Delay, Y1 or Y2 to Global GLB Clock Line

56 Clock Delay, Clock GLB to Global GLB Clock Line

–

–

–

–

1.3

2.3

0.8

10.0

4.3

4.3

2.7

1.3

2.7

1.8

– 10.0 – 10.0 ns

S – 5.3 – 6.4 ns

– 5.3 – 6.4 ns

N – 3.7 – 4.1 ns

SIG 1.4 1.4 2.1 2.1 ns

2.4 2.9 3.6 4.4 ns

DE 0.8 1.8 1.2 2.7 ns

tioy1/2

57 Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line

tiocp

58 Clock Delay, Clock GLB to I/O Cell Global Clock Line

W Global Reset

E tgr

59 Global Reset to GLB and I/O Registers

N 1. Internal Timing Parameters are not tested and are for reference only.

FOR 2. Refer to Timing Model in this data sheet for further details.

0.0 0.3 0.0

0.8 1.8 0.8

– 3.2 –

0.4

1.8

4.5

0.0 0.6 ns

1.2 2.7 ns

– 5.5 ns

Table 2-0037-16/125,100,80

USE ispLSI 1016EA

7

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