AD5687BCPZ-RL7(Rev0) データシートの表示（PDF） - Analog Devices
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AD5687BCPZ-RL7 Datasheet PDF : 24 Pages
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Data Sheet
AD5689/AD5687
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Power-Up Time
1.8 V ≤ VLOGIC < 2.7 V
Min
Max
33
16
16
15
5
5
15
20
16
25
30
20
30
30
4.5
2.7 V ≤ VLOGIC ≤ 5.5 V
Min
Max
20
10
10
10
5
5
10
20
10
15
20
20
30
30
4.5
Unit Description
ns SCLK cycle time
ns SCLK high time
ns SCLK low time
ns SYNC to SCLK falling edge setup time
ns Data setup time
ns Data hold time
ns SCLK falling edge to SYNC rising edge
ns Minimum SYNC high time (update single channel or both channels)
ns SYNC falling edge to SCLK fall ignore
ns LDAC pulse width low
ns SCLK falling edge to LDAC rising edge
ns SCLK falling edge to LDAC falling edge
ns RESET minimum pulse width low
ns RESET pulse activation time
µs Time that is required to exit power-down mode and enter
normal mode of operation; 24th clock edge to 90% of DAC
midscale value with output unloaded
1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 2.7 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
SCLK
SYNC
SDIN
LDAC1
LDAC2
RESET
t9
t1
t8
t4
t3
DB23
t6
t5
t2
t7
DB0
t12
t10
t11
t13
VOUTX
t14
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. 0 | Page 5 of 24
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