AD5687BCPZ-RL7(Rev0) データシートの表示（PDF） - Analog Devices
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AD5687BCPZ-RL7 Datasheet PDF : 24 Pages
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AD5689/AD5687
Data Sheet
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4
and Figure 5. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. VDD =
2.7 V to 5.5 V.
Table 5.
Parameter1
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
1.8 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V
Min
Max
Min
Max
Unit Description
66
40
ns SCLK cycle time
33
20
ns SCLK high time
33
20
ns SCLK low time
33
20
ns SYNC to SCLK falling edge
5
5
ns Data setup time
5
5
ns Data hold time
15
10
ns SCLK falling edge to SYNC rising edge
60
30
ns Minimum SYNC high time
60
30
ns Minimum SYNC high time
36
25
ns SDO data valid from SCLK rising edge
15
10
ns SCLK falling edge to SYNC rising edge
15
10
ns SYNC rising edge to SCLK rising edge
1 Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Circuit and Timing Diagrams
200µA IOL
TO OUTPUT
PIN CL
20pF
VOH (MIN)
200µA IOH
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
SCLK
SYNC
SDIN
SDO
t8
t4
t5
DB23
24
t6
DB0 DB23
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N + 1
t10
DB23
UNDEFINED
INPUT WORD FOR DAC N
Figure 4. Daisy-Chain Timing Diagram
48
t11
t12
DB0
DB0
Rev. 0 | Page 6 of 24
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