AD5687 データシートの表示（PDF） - Analog Devices

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AD5687

Dual, 16-/12-Bit nanoDAC+ with SPI Interface

Analog Devices 

Data Sheet

FEATURES

High relative accuracy (INL): ±2 LSB maximum at 16 bits

Tiny package: 3 mm × 3 mm, 16-lead LFCSP

TUE: ±0.1% of FSR maximum

Offset error: ±1.5 mV maximum

Gain error: ±0.1% of FSR maximum

High drive capability: 20 mA, 0.5 V from supply rails

User-selectable gain of 1 or 2 (GAIN pin)

Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility

50 MHz SPI with readback or daisy chain

Low glitch: 0.5 nV-sec

Low power: 3.3 mW at 3 V

2.7 V to 5.5 V power supply

−40°C to +105°C temperature range

APPLICATIONS

Optical transceivers

Base station power amplifiers

Process control (PLC I/O cards)

Industrial automation

Data acquisition systems

GENERAL DESCRIPTION

The AD5689/AD5687 members of the nanoDAC+™ family are

low power, dual, 16-/12-bit, buffered voltage output digital-to-

analog converters (DACs). The devices include a gain select pin

giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The

AD5689/AD5687 operate from a single 2.7 V to 5.5 V supply, are

guaranteed monotonic by design, and exhibit less than 0.1% FSR

gain error and 1.5 mV offset error performance. Both devices are

available in a 3 mm × 3 mm LFCSP and a TSSOP package.

The AD5689/AD5687 also incorporate a power-on reset circuit

and a RSTSEL pin that ensure that the DAC outputs power up

to zero scale or midscale and remain there until a valid write

takes place. Each part contains a per channel power-down feature

that reduces the current consumption of the device to 4 µA at

3 V while in power-down mode.

The AD5689/AD5687 use a versatile serial peripheral interface

that operates at clock rates up to 50 MHz. Both devices contain

a VLOGIC pin that is intended for 1.8 V/3 V/5 V logic.

Dual, 16-/12-Bit nanoDAC+

with SPI Interface

AD5689/AD5687

VLOGIC

SCLK

SYNC

SDIN

SDO

FUNCTIONAL BLOCK DIAGRAM

VDD

GND

VREF

AD5689/AD5687

INPUT

REGISTER

DAC

REGISTER

STRING

DAC A

INPUT

REGISTER

DAC

REGISTER

STRING

DAC B

BUFFER

BUFFER

VOUTA

VOUTB

LDAC RESET

POWER-ON

RESET

GAIN =

×1/×2

RSTSEL

Figure 1.

GAIN

POWER-

DOWN

LOGIC

Table 1. Related Devices

Interface Reference

SPI

Internal

External

I2C

Internal

16-Bit

AD5689R

AD5689

Not applicable

12-Bit

AD5687R

AD5687

AD5697R

PRODUCT HIGHLIGHTS

1. High Relative Accuracy (INL).

AD5689 (16-bit): ±2 LSB maximum

AD5687 (12-bit): ±1 LSB maximum

2. Excellent DC Performance.

Total unadjusted error: ±0.1% of FSR maximum

Offset error: ±1.5 mV maximum

Gain error: ±0.1% of FSR maximum

3. Two Package Options.

3 mm × 3 mm, 16-lead LFCSP

16-lead TSSOP

Rev. B

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