AD5687 データシートの表示（PDF） - Analog Devices
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AD5687 Datasheet PDF : 24 Pages
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Data Sheet
AD5689/AD5687
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNCE to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNCE Rising Edge
Minimum SYNCE High Time
SYNCE Rising Edge to SYNCE Rising Edge (DAC Register Updates)
SYNCE Falling Edge to SCLK Fall Ignore
LDACE Pulse Width Low
SYNCE Rising Edge to LDACE Rising Edge
SYNCE Rising Edge to LDACE Falling Edge
LDACE Falling Edge to SYNCE Rising Edge
Minimum Pulse Width Low
Pulse Activation Time
Power-Up Time2
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
1.62 V ≤ VLOGIC < 2.7 V
Min
Max
20
10
10
15
5
5
10
20
870
16
15
20
30
840
30
30
4.5
2.7 V ≤ VLOGIC ≤ 5.5 V
Min
Max
20
10
10
10
5
5
10
20
830
10
15
20
30
800
30
30
4.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
1Guaranteed by design and characterization; not production tested.
2 Time to exit power-down to normal mode of operation, SYNCE rising edge to 90% of DAC midscale value, with output unloaded.
t10
t1
SCLK
t8
t3
t2
t7
t14
t4
SYNC
SDIN
1
t9
t6
t5
DB23
DB0
t13
t11
t12
2
t15
VOUT
1
2
t16
Figure 2. Serial Write Operation
Rev. B | Page 5 of 24
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