AD5687 データシートの表示（PDF） - Analog Devices
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AD5687 Datasheet PDF : 24 Pages
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AD5689/AD5687
Data Sheet
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
17B
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4
and Figure 5. VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. VDD =
2.7 V to 5.5 V.
Table 5.
Parameter1
12F
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNCE to SCLK Falling Edge
A
A
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNCE Rising Edge
A
A
Minimum SYNCE High Time
A
A
SDO Data Valid from SCLK Rising Edge
SYNCE Rising Edge to SCLK Falling Edge
A
A
SYNCE Rising Edge to SDO Disable
A
A
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
1.62 V ≤ VLOGIC < 2.7 V
Min
Max
66
33
33
33
5
5
15
60
45
15
60
2.7 V ≤ VLOGIC ≤ 5.5 V
Min
Max
40
20
20
20
5
5
10
30
30
10
60
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 Guaranteed by design and characterization; not production tested.
Circuit and Timing Diagrams
38B
200µA IOL
TO OUTPUT
PIN CL
20pF
VOH (MIN)
200µA IOH
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
t8
t4
t5
DB23
t1
24
t2
t3
t6
DB0 DB23
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N + 1
t9
48
t7
t10
DB0
UNDEFINED
INPUT WORD FOR DAC N
Figure 4. Daisy-Chain Timing Diagram
Rev. B | Page 6 of 24
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