TH8061JDC データシートの表示（PDF） - Melexis Microelectronic Systems
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TH8061JDC Datasheet PDF : 16 Pages
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TH8061
LIN Bus Transceiver with integrated Voltage Regulator
Dynamic Characteristics
All dynamic values of the table below refer to the test-schematic schown in Figure 9...12 - Test Circuit for Dynamic
Characteristics. For the definition of delay and transitions times see Figure 8 - TH8061 Timing Diagram.
(7V ≤ VSUP ≤ 18V, 4.75V ≤ VCC ≤ 5.25V, -40°C ≤ TA ≤ 125°C, unless otherwise specified)
Parameter
Symbol Condition
Min
Typ
Max Unit
RESET
Reset time
tRes
Reset rising time
trr
70
100
140 ms
3.0
6.5
10 µs
LIN-Bus-Interface
Slew rate BUS falling edge [2]
Slew rate BUS rising edge [2]
Symmetry of Slew rate BUS [1]
dV/dTfall
20% ≤ VBUS ≤ 80%
100pF ≤ CBUS ≤ 10nF
-2.5
-2.0
-1.0
V/µs
dV/dTrise
20% ≤ VBUS ≤ 80%
CBUS = 100 pF
1.0
2.0
2.5
V/µs
dV/dTsym
dV/dTrise - dV/dTfall
CBUS = 100 pF
-0.3
0.3
V/µs
Debouncing time BUS
tdebBUS
Hig pulse or low pulse
1.5
2.8
4.0
µs
Symmetry of debouncing BUS
Propagation delay TxD -> BUS [1] [2]
Symmetry of propagation delay
TxD -> BUS [1]
Propagation delay BUS -> RxD [1] [2]
Symmetry of propagation delay
BUS -> RxD [1]
tdebsym
ttrans_pdr,
ttrans_pdf
ttrans_sym
trec_pdr
ttrec_pdf
trec_sym
ttrans_pdr - ttrans_pdf
trec_pdr - trec_pdf
-0.5
-2
-2
0.5
µs
4
µs
2
µs
6
µs
2
µs
Debouncing time TxD [1]
tdeb
Debouncing time EN [1]
tdeb
0.6
1.0
1.5
µs
200
ns
Wake-up-debouncing BUS
tdebWake
25
45
90
µs
______________________________
[1] See timing diagram
[2] See test circuit for dynamic characteristics on page 12 and 13
Datasheet Rev 1.2 Feb 2001
Page 11
www.melexis.com
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