UMA1021AM/C1 データシートの表示（PDF） - Philips Electronics
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UMA1021AM/C1 Datasheet PDF : 16 Pages
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Philips Semiconductors
Low-voltage frequency synthesizer for
radio telephones
Product specification
UMA1021AM
SERIAL BUS TIMING CHARACTERISTICS
VDD1 = VDD2 = VCC = 3 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS MIN.
TYP.
MAX.
Serial programming clock; CLK
tr
rise time
tf
fall time
Tcy
clock cycle time
Enable programming; E
tSTART
tEND
tW
tSU;E
delay to rising clock edge
delay from last falling clock edge
minimum inactive pulse width
enable set-up time to next clock edge
Register serial input data; DATA
tSU;DAT
tHD;DAT
input data to clock set-up time
input data to clock hold time
note 1
−
10
40
−
10
40
100
−
−
40
−
−
−20
−
−
4 000
−
−
20
−
−
20
−
−
20
−
−
Note
1. The minimum pulse width (tW) can be smaller than 4000 ns when the both conditions are fulfilled:
a) Main divider input frequency: fRF > 4--t--4W---7--
b) Reference divider input frequency: fxtal > t--3W---
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
handbook, full pagewtSidUth;DAT
CLK
DATA
MSB
E
tSTART
tHD;DAT
Tcy
tf
tr
tEND tSU;E
LSB
ADDRESS
MBG368
tW
1998 Nov 19
Fig.3 Serial bus timing diagram.
9
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