SPT7935 データシートの表示（PDF） - Cadeka Microcircuits LLC.
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SPT7935 Datasheet PDF : 8 Pages
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Figure 1 – Timing Diagram
Sampling Points
N-1
AIN
CLK
DOUT
N
N+1
tAP
N+2
N+6
N+7
N+8
tD
N-2
N-1
N
GENERAL DESCRIPTION
TYPICAL INTERFACE CIRCUIT
The SPT7935 is an ultra-low power, 12-bit, 20 MSPS ADC.
It has a pipelined architecture and incorporates digital error
correction of the 11 most significant bits. This error correction
ensures good linearity performance for input frequencies up
to Nyquist. The inputs are fully differential, making the device
insensitive to system-level noise. This device can also be
used in a single-ended mode. (See analog input section.)
With the power dissipation roughly proportional to the sam-
pling rate, this device is ideal for very low power applications
in the range of 1 to 20 MSPS.
Figure 2 – Typical Interface Circuit
The SPT7935 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT7935 in
normal circuit operation. The following sections provide
a description of the functions and outline critical perform-
ance criteria to consider for achieving the optimal device
performance.
ANALOG INPUT
The input of the SPT7935 can be configured in various ways
depending on if a single-ended or differential, AC- or DC-
coupled input is desired.
+3.3 V
CLK In
(3 V Logic)
RF In
Ref– In
(+1.15 V)
Ref+ In
(+2.15 V)
+
4.7 µF
4.7 µF
+
.01 µF
11
12
N/C
N/C
90 µA
N/C
GND
9.5 µA
.01 µF
(+1.65 V)
Bias1
Bias2
VCM
GND
68 pF
VIN+
51
VIN–
22 GND
Minicircuit
23
T1-6T
.01 µF
10 µF
+
.01 µF
U1
SPT7935
GND
AGND
+3.3 V
+3.3 V Digital
0.1 µF
1
Decoupling Cap
VDD3 44 (LSB)
D0
D1
D2
D3
D4
Interfacing
D5
3 V Logic
D6
D7
D8
D9
34
33
(MSB)
FB
DGND
Notes: All VDD1, VDD2 and VDD3 should be tied together.
FB = Ferrite Bead; must be placed as close to U1 as possible.
SPT7935
5
7/12/00
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