CDB42L52 データシートの表示（PDF） - Cirrus Logic

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CDB42L52

Evaluation Board for CS42L52

Cirrus Logic 

CDB42L52

1. SYSTEM OVERVIEW

The CDB42L52 platform provides analog and digital interfaces to the CS42L52 and allows for external DSP and

I²C® interconnect. On board power regulators are provided so that only an external +5 V power supply is neces-

sary. Board configuration is done using the Windows PC-compatible GUI to read/write device registers. An FPGA

on the board helps make clock/data routing and CS42L52 configuration easy.

The CDB42L52 schematic set has been partitioned into seven pages and is shown in Figures 4 through 11. “Sys-

tem Connections and Jumpers” on page 13 provides a description of all stake headers and connectors, including

the default factory settings for all jumpers. Section 2. “Software Mode Control” on page 6 provides further configu-

ration details.

1.1 Power

Power is supplied to the evaluation board via the USB connection or by applying +5.0 V to TP2. Jumper J34

allows the user to select the power source. Power (VP) and ground (GND) for the PWM output stages in the

CS42L52 is supplied via binding posts J35 and J4 (respectively) or by standard AAA batteries in locations

BT1, BT2 and BT3. The VP voltage level can be in the range of +1.6 V to +5.25 V. On board regulators and

jumpers allow the user to connect the CODEC’s supplies to +1.65 V, 2.5 V or +3.3 V for VL and +1.65 V or

2.5 V for VD, VA and VA_HP. All voltage inputs must be referenced to ground using the black binding post

J4.

Stake headers/Jumpers and parallel resistors provide a convenient way to measure supply currents to the

CS42L52 for VD, VA, VL, VA_HP and VP supplies. The current is easily calculated by measuring the volt-

age drop across this resistor with its associated jumper removed. NOTE: The stake headers connected in

parallel with these resistors must be shunted with the supplied jumper during normal operation.

WARNING: Please refer to the CS42L52 data sheet for allowable voltage levels.

1.2 Grounding and Power Supply Decoupling

The CS42L52 requires careful attention to power supply and grounding arrangements to optimize perfor-

mance. The CDB42L52 demonstrates these optimal arrangements. Figure 7 on page 16 provides an over-

view of the connections to the CS42L52. Figure 12 on page 21 shows the component placement, Figure 13

on page 22 shows the top layout, and Figure 16 on page 25 shows the bottom layout. Power supply decou-

pling capacitors are located as close as possible to the CS42L52. Extensive use of ground plane fill helps

reduce radiated noise.

1.3 FPGA

The FPGA controls digital signal routing between the CS42L52, CS8406, CS8416, SRC, PLL and the I/O

stake header. It also provides routing control of the system master clock from an on-board oscillator, the

CS8416 and the I/O stake header. The Cirrus FlexGUI software provides full control of the FPGA’s routing

and configuration options. Section 2. “Software Mode Control” on page 6 provides configuration details.

1.4 CS42L52 Audio CODEC

A complete description of the CS42L52 (Figure 4 on page 17) can be found in the CS42L52 product data

sheet.

The CS42L52 is configured using the Cirrus FlexGUI. The device configuration registers are accessible via

the “Register Maps” tab of the Cirrus FlexGUI software. This tab provides low-level control of each bit. For

easier configuration, additional tabs provide high-level control. Section 2. “Software Mode Control” on

page 6 provides configuration details.

DS680DB1

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