ICS84330CI データシートの表示（PDF） - Integrated Device Technology
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ICS84330CI Datasheet PDF : 20 Pages
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ICS84330CI Data Sheet
720MHZ, CRYSTAL-TO-LVPECL FREQUENCY SYNTHESIZER
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
nP_LOAD M
N S_LOAD S_CLOCK S_DATA
X
X
X
X
X
X
L
Data Data
X
X
X
Data Data
L
X
X
H
X
X
L
Data
H
X
X
H
X
X
H
X
X
L
H
X
X
H
NOTE:
L = LOW
H = HIGH
X = Don’t care
= Rising edge transition
= Falling edge transition
L
Data
L
Data
X
X
Data
Conditions
Reset. M and N bits are all set HIGH.
Data on M and N inputs passed directly to the M divider and
N output divider. TEST mode 000.
Data is latched into input registers and remains loaded until next
LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on S_DATA on
each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider and
N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
Table 3B. Programmable VCO Frequency Function Table
VCO Frequency
256
128
64
32
16
8
4
2
1
(MHz)
M Divide
M8
M7
M6
M5
M4
M3
M2
M1
M0
250
125
0
0
1
1
1
1
1
0
1
252
126
0
0
1
1
1
1
1
1
0
254
127
0
0
1
1
1
1
1
0
1
256
128
0
1
0
0
0
0
0
1
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
718
359
1
0
1
1
0
0
1
1
1
720
360
1
0
1
1
0
1
0
0
0
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
Table 3C. Programmable Output DividerFunction Table
Inputs
N1
N0
N Divider Value
0
0
2
0
1
4
1
0
8
1
1
1
Output Frequency (MHz)
Minimum
Maximum
125
360
62.5
180
31.25
90
250
720
ICS84330CVI REVISION A JANUARY 7, 2011
4
©2011 Integrated Device Technology, Inc.
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