TMC2249A データシートの表示（PDF） - Raytheon Company

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TMC2249A

Digital Mixer 12 x 12 bit, 60 MHz

Raytheon Company 

TMC2249A

PRODUCT SPECIFICATION

Pin Descriptions (continued)

Pin Number

Pin Name

PGA

MQFP

Pin Function Description

Controls

ENA-END N13, N2, C12,

A3

60, 33, 89, 116

Input Enables. Input data presented to port i11-0 (i=A,B,C, or D) are

latched into delay pipeline i, and data already in pipeline i advance

by one register position, on each rising edge of CLK for which ENi is

LOW. When ENi is HIGH, the data in pipeline i do not move and the

value at the input port i will be lost before it reaches the multiplier.

NEG1,2

B1, D3

3, 4

Negate. The products of the multipliers are negated causing a

subtraction to be performed during the internal summation of

products, when the NEGate controls are HIGH, NEG1 negates the

product A x B, while NEG2 acts on the output of the multiplier which

generates the product C x D. When the length controls ADEL–DDEL

are set to zero, these controls indicate the operation to be performed

on data input during the same clock. As nonzero values for ADEL–

DDEL do not affect the pipelining of these controls, their effect is not

synchronous with the data input in these cases.

RND

C2

5

Round. When the rounding control is HIGH, the 24-bit sum of

products resulting from data input during that clock is rounded to 16

bits. When enabled rounding is automatically performed only during

the first cycle of each accumulation sequence, to avoid the

accumulation of roundoff errors.

FT

E11

84

Feedthrough. When the Feedthrough control is HIGH, the pipeline

delay through the cascade data path is minimized to simplify the

cascading of multiple devices. When FT is LOW and ADEL through

DDEL are all set to 0, the data inputs are aligned, such that

S(n+6) = CAS(n) + A(n)B(n) + C(n)D(n). See Table 2.

CASEN

D13

83

Cascade Enable. Data presented at the cascade data input port are

latched and accumulated internally when the input enable CASEN

during that clock is LOW. When CASEN is HIGH, the cascade input

port is ignored.

ACC

B2

2

Accumulate. When the registered ACCumulator control is LOW, no

internal accumulation will be performed on the data input during the

current clock, effectively clearing the prior accumulated sum. When

ACC is HIGH, the internal accumulator adds the emerging product

to the sum of the previous products and RND is disabled.

SWAP

K3

28

Swap Output Words. The user may access both the most and

least-significant 16 bits of the 24-bit accumulator by utilizing SWAP.

Normal operation of the device, with SWAP = HIGH, outputs the

most significant word. Setting SWAP = LOW puts a double-register

structure into "toggle" mode, allowing the user to examine the LSW

on alternate clocks. New output data will not be clocked into the

output registers until SWAP returns HIGH.

OE

M1

27

Output Enable. Data currently in the output registers is available at

the output bus S15-0 when the asynchronous Output Enable is LOW.

When OE is HIGH, the outputs are in the high-impedance state.

No Connect

L12

65

Do Not Connect

D4

Index Pin (optional)

6

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