HI5660 データシートの表示（PDF） - Renesas Electronics
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HI5660 Datasheet PDF : 9 Pages
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HI5660
Timing Diagrams
CLK
50%
D7-D0
IOUT
1/2 LSB ERROR BAND
tSETT
tPD
FIGURE 1. OUTPUT SETTLING TIME DIAGRAM
V
GLITCH AREA = 1/2 (H x W)
HEIGHT (H)
WIDTH (W)
t (ps)
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
CLK
D7-D0
IOUT
tPW1
tPW2
tSU
tSU
tSU
tHLD
tHLD
tHLD
tPD
tSETT
50%
tPD
tSETT
tPD
tSETT
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
FN4521 Rev 7.00
July 2004
Page 6 of 9
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