SP9601JN データシートの表示（PDF） - Signal Processing Technologies
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SP9601JN Datasheet PDF : 9 Pages
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SPECIFICATIONS (continued)
(Typical at 25˚C; TMIN ≤ TA≤TMAX; VDD = +5V, VSS = -5V, VREF = +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
MIN. TYP. MAX.
UNITS
CONDITIONS
POWER REQUIREMENTS
VDD
-J, -K
-A, -B
VSS
-J, -K
-A, -B
Power Dissipation
SWITCHING
0.2
0.3
0.2
0.45
0.2
0.3
0.2
0.45
2
Note 5
+5V, ±3%; Note 4, 5
mA
mA
-5V, ±3%; Note 4, 5
mA
mA
mW
CHARACTERISTICS
CS Setup Time
(tCSS)
25
ns
SCLK Fall to CS
Fall Hold Time
(tCSH0)
20
ns
SCLK Fall to CS Rise
Hold Time
(tCSH1)
0
ns
SCLK High Width
(tCH)
40
ns
SCLK Low Width
(tCL)
40
ns
DIN Setup Time
(tDS)
50
ns
DIN Hold Time
(tDH)
0
ns
CS High Pulse Width
(tCSW)
30
ns
ENVIRONMENTAL AND
MECHANICAL
Operating Temperature
-J, -K
-A, -B
Storage
Package
0
+70
°C
-40
+85
°C
-60
+150
°C
–_N
8-pin Plastic DIP
–_S
8-pin 0.15" SOIC
Notes:
1.
2.
3.
4.
Integral Linearity, for the SP9601, is measured as the arithmetic mean value of the magnitudes of
the greatest positive deviation and the greatest negative deviation from the theoretical value for any
given input condition.
Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
1 LSB = 2*VREF/4,096.
VREF = 0V.
5.
The following power up sequence is recommended: VSS (-5V), Vdd (+5V), VREF.
SP9601DS/02
SP9601 12-Bit, Low-Power Voltage Output
3
© Copyright 2000 Sipex Corporation
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