SP9601JN データシートの表示（PDF） - Signal Processing Technologies

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SP9601JN

12–Bit, Low Power Voltage Output D/A Converter

Signal Processing Technologies 

PINOUT – 8-PIN PLASTIC DIP & SOIC

VOUT 1

VDD 2

SCLK 3

DIN 4

SP9601

8 VREF

7 GND

6 VSS

5 CS

PIN ASSIGNMENTS

Pin 1- VOUT – Voltage Output.

Pin 2- V – +5V Power Supply Input.

DD

Pin 3- SCLK – Serial Clock Input.

Pin 4- DIN – Serial Data Input.

Pin 5- CS – Chip Select Input.

Pin 6- VSS– –5V Power Supply Input.

Pin 7- GND – Ground.

Pin 8- VREF – Reference Input.

FEATURES...

The SP9601 is a low power 12–Bit Digital-to-

Analog Converter. The converter features ±4.5V

output swings with ±5V supplies. The input

coding format used is standard offset binary,

Table 1.

This Digital-to Analog Converter uses a stan-

dard 3–wire interface compatible with SPI™,

QSPI™ and Microwire™. The output settling

time is specified at 30µs to full 12-bit accuracy

when driving a 5KΩ, 50pF load combination.

The SP9601 Digital-to-Analog Converter is

ideally suited for applications such as ATE,

process controllers, robotics and instrumenta-

tion. The SP9601 is available in an 8-pin 0.15"

SOIC and 0.3" PDIP packages, specified over

commercial and industrial temperature ranges.

THEORY OF OPERATION

The SP9601 consists of four main functional

blocks – the input shift register, DAC register,

12-Bit D/A converter and a bipolar output volt-

age amplifier, Figure 1.

The input shift register is used to convert the

serial input data stream to a parallel 12–Bit

digital word. The input data is shifted on posi-

tive clock (SCLK) edges when the Chip Select

(CS) signal is in the “low” state. The MSB is

loaded first and LSB last. No shifting of the

input data occurs when the Chip Select (CS)

signal is in the “high” state.

The DAC register is used to store the digital

word which is sent to the DAC. Its value is

updated on the positive transition of the Chip

Select (CS) signal.

In order to reduce the DAC full scale output

sensitivity to the large weighting of the MSB's

found in conventional R-2R resistor ladders, the

3 MSB's are decoded into 8 equally weighted

levels. This reduces the contribution of each bit

by a factor of 4, thus, reducing the output sensi-

tivity to mismatches in resistors and switches by

the same amount. Linearity errors and stability

are both improved for the same reasons.

The DAC itself is implemented with precision

thin-film resistors and CMOS transmission gate

switches. The resistor network is laser-trimmed

to achieve better than 12–Bit accuracy. The D/

A converter is used to convert the 12-bit input

word to a precision voltage.

INPUT

MSB

LSB

OUTPUT

1111

1111

1000

1000

1111

1111

0000

0000

1111

1110

0001

0000

VREF - 1 LSB

VREF - 2 LSB

0 + 1 LSB

0

0000

0000

0000 0001

0000 0000

1 LSB =

-VREF + 1 LSB

-VREF

2 VREF

2 12

Table 1. Offset Binary Coding

SP9601DS/02

SP9601 12-Bit, Low-Power Voltage Output

4

© Copyright 2000 Sipex Corporation

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