MT9300B データシートの表示（PDF） - Zarlink Semiconductor Inc

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MT9300B

Multi-Channel Voice Echo Canceller

Zarlink Semiconductor Inc 

MT9300B

Data Sheet

Pin Description (continued)

Pin #

208-Ball LBGA

A4

G2

H2

K3

K4

M2

M1

N1

P1

N2

R3

C6,D6,J3,J4,N12,P12, G13,G14

160 Pin Name

MQFP

Description

112

C4i Serial Clock (Input). 4.096 MHz serial clock for shifting

data in/out on the serial streams (Rin, Sin, Rout, Sout).

140

MCLK Master Clock (Input). Nominal 10 MHz or 20 MHz Master

Clock input. May be connected to an asynchronous

(relative to frame signal) clock source.

143

Fsel Frequency select (Input). This input selects the Master

Clock frequency operation. When Fsel pin is low, nominal

19.2 MHz Master Clock input must be applied. When Fsel

pin is high, nominal 9.6 MHz Master Clock input must be

applied.

146 PLLVSS PLL Ground. Must be connected to VSS.

147 PLLVDD PLL Power Supply. Must be connected to VDD1.

152

TMS Test Mode Select (3.3 V Input). JTAG signal that controls

the state transitions of the TAP controller. This pin is pulled

high by an internal pull-up when not driven.

153

TDI Test Serial Data In (3.3 V Input). JTAG serial test

instructions and data are shifted in on this pin. This pin is

pulled high by an internal pull-up when not driven.

154

TDO Test Serial Data Out (Output). JTAG serial data is output

on this pin on the falling edge of TCK. This pin is held in

high impedance state when JTAG scan is not enabled.

155

TCK Test Clock (3.3 V Input). Provides the clock to the JTAG

test logic.

156

TRST Test Reset (3.3 V Input). Asynchronously initializes the

JTAG TAP controller by putting it in the Test-Logic-Reset

state. This pin should be pulsed low on power-up or held

low, to ensure that the MT9300B is in the normal functional

mode. This pin is pulled by an internal pull-down when not

driven.

158 RESET Device Reset (Schmitt Trigger Input). An active low

resets the device and puts the MT9300B into a low-power

stand-by mode.

When the RESET pin is returned to logic high and a

clock is applied to the MCLK pin, the device will

automatically execute initialization routines, which preset

all the Control and Status Registers to their default

power-up values.

VDD2

These LBGA pins should be wired to VDD2= 1.8 V for

FUTURE USE. If the customer does not intend to use

future generation of the device, then these pins should

be NO CONNECTS

7

Zarlink Semiconductor Inc.

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