MT9300B データシートの表示（PDF） - Zarlink Semiconductor Inc

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MT9300B

Multi-Channel Voice Echo Canceller

Zarlink Semiconductor Inc 

MT9300B

Data Sheet

Device Overview

The MT9300B architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo

cancellers, Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay or

Back-to-Back configurations. In Normal configuration, a group of echo cancellers provides two channels of 64ms

echo cancellation, which run independently on different channels. In Extended Delay configuration, a group of

echo cancellers achieves 128ms of echo cancellation by cascading the two echo cancellers (A & B). In Back-to-

Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both

directions in a single channel, providing full-duplex 64ms echo cancellation.

Each echo canceller contains the following main elements (see Figure 4).

• Adaptive Filter for estimating the echo channel

• Subtractor for cancelling the echo

• Double-Talk detector for disabling the filter adaptation during periods of double-talk

• Path Change detector for fast reconvergence on major echo path changes

• Instability Detector to combat oscillation in very low ERL environments

• Non-Linear Processor for suppression of residual echo

• Disable Tone Detectors for detecting valid disable tones at send and receive path inputs

• Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals

• Offset Null filters for removing the DC component in PCM channels

• 12dB attenuator for signal attenuation

• Parallel controller interface compatible with Motorola microcontrollers

• PCM encoder/decoder compatible with µ/A-Law ITU-T G.711 or Sign-Magnitude coding

Each echo canceller in the MT9300B has four functional states: Mute, Bypass, Disable Adaptation and Enable

Adaptation. These are explained in the section entitled Echo Canceller Functional States.

Sin

(channel N)

µ/A-Law/

Linear

Offset

Null

+

-

Non-Linear

Processor

Linear/

µ/A-Law

GCI

PORT2

Disable Tone

Detector

Programmable

Bypass

Microprocessor

Interface

Double-Talk

Detector

MuteS

Path Change

Detector

Instability

Detector

Narrow-Band

Detector

MuteR

Disable Tone

Detector

Rout

(channel N)

Linear/

µ/A-Law

12dB

Attenuator

Offset

Null

µ/A-Law/

Linear

Sout

(channel N)

GCI

PORT1

Rin

(channel N)

Echo Canceller (N), where 0 ≤

N ≤ 31

Figure 4 - Echo Canceller Functional Block Diagram

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Zarlink Semiconductor Inc.

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