HI5812 データシートの表示（PDF） - Renesas Electronics

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HI5812

CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold

Renesas Electronics 

HI5812

resistance. The time constant is 160ns. To charge this capacitor

from an external “zero ” source to 0.5 LSB (1/8192), the

charging time must be at least 9 time constants or 1.4s. The

maximum source impedance (RSOURCE Max) for a 4s

acquisition time settling to within 0.5LSB is 750.

If the clock frequency was slower, or the converter was not

restarted immediately (causing a longer sample time), a higher

source impedance could be tolerated.

VIN

RSW  420

CSAMPLE  380pF

RSOURCE

RSOURCE(MAX) = -C----S----A----M-----P----L-–--E-t--A-I--n-C----Q-2----–-----N-----+----1------ – RSW

FIGURE 19. ANALOG INPUT MODEL IN TRACK MODE

Reference Input

The reference input VREF+ should be driven from a low

impedance source and be well decoupled.

As shown in Figure 20, current spikes are generated on the

reference pin during each bit test of the successive

approximation part of the conversion cycle as the charge-

balancing capacitors are switched between VREF- and VREF+

(clock periods 5 - 14). These current spikes must settle

completely during each bit test of the conversion to not

degrade the accuracy of the converter. Therefore VREF+ and

VREF- should be well bypassed. Reference input VREF- is

normally connected directly to the analog ground plane. If

VREF- is biased for nulling the converters offset it must be

stable during the conversion cycle.

20mA

IREF+ 10mA

0mA

5V

CLK

0V

5V

DRDY

0V

2s/DIV.

CONDITIONS: VDD = VAA+ = 5.0V, VREF+ = 4.608V,

VIN = 2.3V, CLK = 750kHz, TA = 25oC

FIGURE 20. TYPICAL REFERENCE INPUT CURRENT

The HI5812 is specified with a 4.608V reference, however, it

will operate with a reference down to 3V having a slight

degradation in performance. A typical graph of accuracy vs

reference voltage is presented.

Full Scale and Offset Adjustment

In many applications the accuracy of the HI5812 would be

sufficient without any adjustments. In applications where

accuracy is of utmost importance full scale and offset errors

may be adjusted to zero.

The VREF+ and VREF- pins reference the two ends of the

analog input range and may be used for offset and full scale

adjustments. In a typical system the VREF- might be returned

to a clean ground, and the offset adjustment done on an input

amplifier. VREF+ would then be adjusted to null out the full

scale error. When this is not possible, the VREF- input can be

adjusted to null the offset error, however, VREF- must be well

decoupled.

Full scale and offset error can also be adjusted to zero in the

signal conditioning amplifier driving the analog input (VIN).

Control Signal

The HI5812 may be synchronized from an external source by

using the STRT (Start Conversion) input to initiate conversion,

or if STRT is tied low, may be allowed to free run. Each

conversion cycle takes 15 clock periods.

The input is tracked from clock period 1 through period 3, then

disconnected as the successive approximation takes place.

After the start of the next period 1 (specified by tD data), the

output is updated.

The DRDY (Data Ready) status output goes high (specified by

tD1DRDY) after the start of clock period 1, and returns low

(specified by tD2DRDY) after the start of clock period 2.

The 12 data bits are available in parallel on three-state bus

driver outputs. When low, the OEM input enables the most

significant byte (D4 through D11) while the OEL input enables

the four least significant bits (D0 - D3). tEN and tDIS specify the

output enable and disable times.

If the output data is to be latched externally, either the trailing

edge of data ready or the next falling edge of the clock after

data ready goes high can be used.

When STRT input is used to initiate conversions, operation is

slightly different depending on whether an internal or external

clock is used.

Figure 3 illustrates operation with an internal clock. If the STRT

signal is removed (at least tRSTRT) before clock period 1, and

is not reapplied during that period, the clock will shut off after

entering period 2. The input will continue to track and the

DRDY output will remain high during this time.

A low signal applied to STRT (at least tWSTRT wide) can now

initiate a new conversion. The STRT signal (after a delay of

(tDSTRT)) causes the clock to restart.

FN3214 Rev 6.00

March 31, 2005

Page 11 of 16

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