CDB4385A データシートの表示（PDF） - Cirrus Logic

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CDB4385A

Evaluation Board for CS4385A

Cirrus Logic 

CDB4385A

CDB4385A SYSTEM OVERVIEW

The CDB4385A evaluation board provides a quick method for evaluating the CS4385A. The CS8416 digital audio

interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test

equipment. The evaluation board also allows the user to supply external PCM or DSD clocks and data through PCB

headers for system development.

The CDB4385A schematic is partitioned into the ten schematics shown in Figures 44 through 53. Each partitioned

schematic is represented in the system diagram shown in Figure 43. Notice that the system diagram also includes

the interconnections between the partitioned schematics.

1. CS4385A DIGITAL-TO-ANALOG CONVERTER

A description of the CS4385A is included in the CS4385A datasheet.

2. CS8416 DIGITAL AUDIO RECEIVER

The system receives and decodes the standard S/PDIF data format using a CS8416 digital audio receiver

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serial bit clock, serial data, left-right

The operation of the CS8416 and a

clock, and a 128/256 Fs mas-

discussion of the digital audio

interface is included in the CS8416 datasheet.

The evaluation board has been designed such that the input can be either optical or coaxial, see Figure 49. How-

ever, both inputs cannot be driven simultaneously.

Switch position 7 of S1 sets the output MCLK-to-LRCK ratio of the CS8416. This switch should be set to 256 (closed)

for inputs Fs≤96 kHz and 128 (open) for Fs≥64 kHz. The CS8416 must be manually reset using ‘HW RST’ (S2)

or through the software when this switch is changed.

3. INPUT FOR CLOCKS AND DATA

The evaluation board has been designed to allow interfacing to external systems via headers J11 and J7. Header

J11 allows the evaluation board to accept externally generated PCM clocks and data. The schematic for the

clock/data input is shown in Figure 50. Switch position 6 of S1 selects the source as either CS8416 (open) or header

J11 (closed).

Header J7 allows the evaluation board to accept externally generated DSD data and clocks. The schematic for the

clock/data input is shown in Figure 50. A synchronous MCLK must still be provided via Header J11. Switch position

8 of S1 selects either PCM (open) or DSD (closed).

Please see the CS4385A datasheet for more information.

4. INPUT FOR CONTROL DATA

The evaluation board can be run in either a standalone mode or with a PC. Standalone mode uses the CS4385A in

hardware mode and the mode pins are configured using switch positions 1 through 5 of S1. PC mode uses software

to setup the CS4385A through I²C using the PC’s serial port. PC mode is automatically selected when the serial port

(RS232) is attached and the CDB4385A software is running (USB operation is not available at this time).

Header J15 offers the option for external input of RST and SPI™/I²C clocks and data. The board is setup from the

factory to use the on-board microcontroller in conjunction with the supplied software. To use an external control

source, remove

are on the right

the shunts on J15 and

side. R116 and R119

place a

should

ribbon cable so the signal lines are on the center

be populated with 2-kΩ resistors when using an

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which does not already provide pull-ups.

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DS837DB1

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