CDB5345 データシートの表示（PDF） - Cirrus Logic

部品番号

コンポーネント説明

メーカー

CDB5345

Evaluation Board for CS5345

Cirrus Logic 

CDB5345

2. SYSTEM CLOCKS AND DATA

The CDB5345 implements comprehensive clock routing capabilities. Configuration of the clock routing can be easily

achieved using the controls within the Board Controls group box on the CDB5345 Controls tab in the GUI software

application.

2.1 Clock Routing

The master clock signal (MCLK) may be sourced from the canned oscillator (Y1) or the PCM1 I/O header

(J10)

The sub-clock signals (SCLK and LRCK) may be sourced from the CS5345 in master mode, the CS8406 in

master mode, or the PCM1 I/O header.

Clock routing configuration is achieved using the MCLK Source and Subclock Source controls within the

Board Controls group box on the CDB5345 Controls tab in the GUI software application.

2.2 Data Routing

The serial data output of the CS5345 is routed to both the CS8406 S/PDIF transmitter and the PCM1 I/O

header. No user configuration of the serial data routing is required.

6

DS658DB1

Share Link: