FS6370 データシートの表示（PDF） - AMI Semiconductor
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FS6370 Datasheet PDF : 25 Pages
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FS6370-01
EEPROM Programmable 3-PLL Clock Generator IC
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
TYPE
NAME
DESCRIPTION
1
P
VSS
Ground
2
DIU
SEL_CD
Selects one of two programmed PLL C, Mux C/D, and Post Divider C/D combinations
3
DIU
PD/SCL
Power-Down Input (Run Mode) or
Serial Interface Clock Input (Program Mode)
4
P
VSS
Ground
5
AI
XIN
Crystal Oscillator Feedback
6
AO
XOUT
Crystal Oscillator Drive
7
DIUO
OE/SDA
Output Enable Input (Run Mode) or
Serial Interface Data Input/Output (Program Mode)
8
P
VDD
Power Supply (5V to 3.3V)
9
DIU
MODE
Selects either Program Mode (low) or Run Mode (high)
10
DO
CLK_D
D Clock Output
11
P
VSS
Ground
12
DO
CLK_C
C Clock Output
13
DO
CLK_B
B Clock Output
14
P
VDD
Power Supply (5V to 3.3V)
15
DO
CLK_A
A Clock Output
16
P
VDD
Power Supply (5V to 3.3V)
3.0 Functional Block Description
3.1 Phase Locked Loops
Each of the three on-chip phase-locked loops (PLLs) is a
standard phase- and frequency-locked loop architecture
that multiplies a reference frequency to a desired fre-
quency by a ratio of integers. This frequency multiplica-
tion is exact.
As shown in Figure 3, each PLL consists of a Reference
Divider, a Phase-Frequency Detector (PFD), a charge
pump, an internal loop filter, a Voltage-Controlled Oscil-
lator (VCO), and a Feedback Divider.
During operation, the reference frequency (fREF), gener-
ated by the on-board crystal oscillator, is first reduced by
the Reference Divider. The divider value is often referred
to as the modulus, and is denoted as NR for the Refer-
ence Divider. The divided reference is fed into the PFD.
The PFD controls the frequency of the VCO (fVCO)
through the charge pump and loop filter. The VCO pro-
vides a high-speed, low noise, continuously variable fre-
quency clock source for the PLL. The output of the VCO
is fed back to the PFD through the Feedback Divider (the
modulus is denoted by NF) to close the loop.
Figure 3: PLL Block Diagram
REFDIV[7:0]
fREF Reference
Divider
(NR)
CP
Phase-
Frequency
Detector
UP
Charge
Pump
DOWN
fPD
FBKDIV[10:0]
Feedback
Divider (NF)
LFTC
Loop
Filter
Voltage fVCO
Controlled
Oscillator
2
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