FS6370 データシートの表示（PDF） - AMI Semiconductor
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FS6370 Datasheet PDF : 25 Pages
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FS6370-01
EEPROM Programmable 3-PLL Clock Generator IC
3.2 Post Divider Muxes
As shown in Figure 2, a mux in front of each post divider
stage can select from any one of the three PLL frequen-
cies or the reference frequency. The mux selection is
controlled by bits in the EEPROM or the control registers.
The input frequency on two of the four multiplexers
(Muxes C and D in Figure 2) can be altered without re-
programming by a logic-level input on the SEL_CD pin.
3.3 Post Dividers
A post divider performs several useful functions. First, it
allows the VCO to be operated in a narrower range of
speeds compared to the variety of output clock speeds
that the device is required to generate. Second, it
changes the basic PLL equation to
f CLK
=
f REF
ççèæ
N
N
F
R
÷÷øöççèæ
1
NP
÷÷øö
where NP is the post divider modulus. The extra integer in
the denominator permits more flexibility in the program-
ming of the loop for many applications where frequencies
must be achieved exactly.
The modulus on two of the four post dividers (Post Divid-
ers C and D in Figure 2) can be altered without repro-
gramming by a logic level on the SEL_CD pin.
4.0 Device Operation
The FS6370 has two modes of operation:
§ Program Mode, during which either the EEPROM or
the FS6370 control registers can be programmed di-
rectly with the desired PLL settings, and
§ Run Mode, where the PLL settings stored the
EEPROM are transferred to the FS6370 control reg-
isters on power-up, and the device then operates
based on those settings.
Note that the EEPROM locations are not physically the
same registers used to control the FS6370.
Direct access to either the EEPROM or the FS6370 con-
trol registers is achieved in Program Mode. The
EEPROM register contents are automatically transferred
to the FS6370 control registers in normal device opera-
tion (Run Mode).
4.1 MODE Pin
The MODE pin controls the mode of operation. A logic-
low places the FS6370 in Program Mode. A logic-high
puts the device in Run Mode. A pull-up on this pin de-
faults the device into Run Mode.
Reprogramming of either the control registers or the
EEPROM is permitted at any time if the MODE pin is a
logic-low.
Note, however, that a logic-high state on the MODE pin is
latched so that only one transfer of EEPROM data to the
FS6370 control registers can occur. If a second transfer
of EEPROM data into the FS6370 is desired, power
(VDD) must be removed and reapplied to the device.
The MODE pin also controls the function of the PD/SCL
and OE/SDA pins. In Run Mode, these two pins function
as power-down (PD) and output enable (OE) controls. In
Program Mode, the pins function as the I2C interface for
clock (SCL) and data (SDA).
4.2 SEL_CD Pin
The SEL_CD pin provides a way to alter the operation of
PLL C, Muxes C and D, and Post Dividers C and D with-
out having to reprogram the device. A logic-low on the
SEL_CD pin selects the control bits with a “C1” or “D1”
notation, per Table 3. A logic-high on the SEL_CD pin
selects the control bits with “C2” or “D2” notation, per
Table 3.
Note that changing between two running frequencies us-
ing the SEL_CD pin may produce glitches in the output,
especially if the post-divider(s) is/are altered.
4.3 Oscillator Overdrive
For applications where an external reference clock is
provided (and the crystal oscillator is not required), the
reference clock should be connected to XOUT and XIN
must be left unconnected (float).
For best results, make sure the reference clock signal is
as jitter-free as possible, can drive a 40pF load with fast
rise and fall times, and can swing rail-to-rail.
If the reference clock is not a rail-to-rail signal, the refer-
ence must be AC coupled to XOUT through a 0.01µF or
0.1µF capacitor. A minimum 1V peak-to-peak signal is
required to drive the internal differential oscillator buffer.
4
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