AS3524A-ZC21T データシートの表示（PDF） - austriamicrosystems AG

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AS3524A-ZC21T

Advanced Audio Processor System

austriamicrosystems AG 

AS3524 C21 / C22

Data Sheet, Confidential

austriamicrosystems

4.2 Operating Conditions

4.2.1 Supply Voltages

Following supply voltages for the digital system are generated by internal LDOs.

Table 2 Operating conditions for internal generated supply voltages

Symbol

VDDperi

VDDmem

VDDcore

Parameter

VDDcoreana

VDDAPLL

USBVDDA33T

USBVDDA33C

Difference of Negative

Supplies

vss_peri, vss_core,

vss_core_ana, vss_mem,

vssa_pll, usb_vssa33c,

usb_vssa33t,

Min

Max

Unit

Note

3.0

3.6

V digital periphery supply voltage

1.75

3.4

V digital IO supply for MPMC PADs

1.08

1.25

1.08

1.25

V digital core supply voltage

see Note (1)

V core supply for critical blocks (1-TRAM)

1.08

1.25

V core supply forPLLA, PLLB

3.15

3.45

3.15

3.45

-0.1

0.1

V USB analog supply transmit block

to be connected to UVDD

V USB analog supply common block

to be connected to UVDD

V To achieve good performance, the

negative supply terminals should be

connected to low impedance ground

plane.

Note(s)

(1) For the VDD_CORE supply, voltage scaling should be applied to optimize power consumption

and CPU speed performance. For normal operation with fclk (CPU ARM-922T clock) frequencies

below 200 MHz, CVDD (supply of VDD_CORE) can be set to a lower value of 1.10 V. Only for setting

fclk of the CPU to clock frequencies above 200 MHz, the VDD_CORE supply voltage must be set to

1.20 V typical conditions.

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