N386SX データシートの表示（PDF） - Intel

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N386SX

Intel387™ SX MATH COPROCESSOR

Intel 

CONTENTS

PAGE

FIGURES

Figure 1-1 Intel387 SX Math

CoProcessor Pinout

5

Figure 2-1 Intel387 SX Math

CoProcessor Block

Diagram

7

Figure 3-1 Intel 386 SX CPU and

Intel387 Math CoProcessor

Register Set

11

Figure 3-2 Status Word

12

Figure 3-3 Control Word

15

Figure 3-4 Tag Word Register

16

Figure 3-5 Instruction and Data Pointer

Image in Memory 32-Bit

Protected Mode Format

17

Figure 3-6 Instruction and Data Pointer

Image in Memory 16-Bit

Protected Mode Format

17

Figure 3-7 Instruction and Data Pointer

Image in Memory 32-Bit

Real Mode Format

17

Figure 3-8 Instruction and Data Pointer

Image in Memory 16-Bit

Real Mode Format

18

Figure 4-1 Intel386 SX CPU and

Intel387 SX Math

CoProcessor System

Configuration

25

Figure 5-1 Bus State Diagram

28

Figure 5-2 Non-Pipelined Read and

Write Cycles

29

Figure 5-3 Fastest Transition to and

from Pipelined Cycles

30

Figure 5-4 Pipelined Cycles with Wait

States

31

Figure 5-5 BUSY and PEREQ Timing

Relationship

32

Figure 7-1a Typical Output Valid Delay

vs Load Capacitance at Max

Operating Temperature

37

Figure 7-1b Typical Output Slew Time vs

Load Capacitance at Max

Operating Temperature

37

Figure 7-1c Maximum ICC vs

Frequency

37

CONTENTS

Figure 7-2

CPUCLK2 NUMCLK2

Waveform and

Measurement Points for

Input Output

Figure 7-3 Output Signals

Figure 7-4 Input and I O Signals

Figure 7-5 RESET Signal

Figure 7-6 Float from STEN

Figure 7-7 Other Parameters

PAGE

38

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TABLES

Table 1-1 Pin Cross Reference

Functional Grouping

5

Table 3-1 Condition Code

Interpretation

13

Table 3-2 Condition Code Interpretation

after FPREM and FPREM1

Instructions

14

Table 3-3 Condition Code Resulting

from Comparison

14

Table 3-4 Condition Code Defining

Operand Class

14

Table 3-5 Mapping Condition Codes to

Intel386 CPU Flag Bits

14

Table 3-6 Intel387 SX Math

CoProcessor Data Type

Representation in Memory 19

Table 3-7 CPU Interrupt Vectors

Reserve for Math

CoProcessor

20

Table 3-8 Intel387 SX Math

CoProcessor Exceptions

20

Table 4-1 Pin Summary

22

Table 4-2 Output Pin Status during

Reset

23

Table 4-3 Bus Cycle Definition

26

Table 6-1 Thermal Resistances

( C Watt) iJC and iJA

33

Table 6-2 Maximum TA at Various

Airflows

33

Table 7-1 D C Specifications

34

Table 7-2a Timing Requirements of the

Bus Interface Unit

35

Table 7-2b Timing Requirements of the

Execution Unit

36

Table 7-2c Other AC Parameters

36

Table 8-1 Instruction Formats

41

4

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