CMX661 データシートの表示（PDF） - MX-COM Inc

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CMX661

Pair Gain Dual SPM Detector

MX-COM Inc  

Pair Gain Dual SPM Detector

Page 6 of 14

CMX661 Advance Information

4. General Description

4.1 Description of Blocks

4.1.1 Crystal Oscillator and Clock Dividers

These circuits derive the internal logic clocks, decode frequencies, and transmit frequencies by frequency

division of a reference frequency that is generated by the on-chip crystal oscillator. The only external

component required is a 3.579545MHz crystal, which should be connected across the XTAL and XTALN pins.

All other oscillator components are on-chip.

4.1.2 Input Operational Amplifiers

The input signals are applied to the CMX661 via these amplifiers, which use the external components shown

in Figure 2. The external gain setting components should be calculated by the method described in

Section 5.4, using the values obtained from Figure 5.

4.1.3 SPM Tone Bandpass Filter

These are tone bandpass/audio reject filters automatically centered on the system frequency (12kHz or

16kHz) being detected. Their gain is constant so the internal device sensitivity is also constant.

4.1.4 Level Detection and Pulse Generator Circuits

The outputs from the bandpass filters are input to these circuits that perform the signal level discrimination

function for the CMX661. Signals that fulfill the system level requirements cause a stream of digital pulses,

one per 32 cycles of input signal, to be generated. These pulses are sent to the period measurement circuitry.

4.1.5 Period Measurement Logic

This digital circuit block inputs the stream of pulses from the level detection circuits and measures their

repetition rate against a predetermined maximum and minimum. Because each pulse from the level detect

circuit occurs once per 32 cycles of input signal, this has the effect of averaging the input signal period over

this number of cycles. A valid SPM tone is recognized when 3 successive correctly spaced pulses are

received. This causes a signal to appear immediately at the relevant channel output signifying receipt of a

valid SPM signal. Depending upon the frequency, within the legal bandwidth, received, the CMX661 should

respond within 10-15ms (see Section 6 and Figure 4).

4.1.6 Output Enable Circuits

These enable the output logic pins ‘Channel 1 Output’ and ‘Channel 2 Output’. These outputs can be made

high impedance by setting the OP ENABLEN pin high. When enabled, a high (logic ‘1’) indicates the tone is

absent, a low (logic ‘0’) indicates the tone is present.

4.2 Operating States

The CMX661 is a dual-channel SPM detector where both detectors are set to the same bandwidth and system

frequency (12kHz or 16kHz). The sensitivity of each detector is set via external components. The decode

bandwidths can be set to ±1.5%, ±3%, ±5% and ±7.5% of the nominal tone frequency by means of the D0 and

D1 logic inputs and the system frequency is set by the SYSTEM SELECT logic input. Each decoder logic

output has a very short response and deresponse time so that it forms an ‘envelope’ of the input tone. Host

µC systems must decide whether the received signal fulfils the system tone pulse length requirements. The

outputs can be set to a high impedance state for device multiplexing by use of the OP ENABLEN pin (logic '1'

gives a high impedance state on the decoder outputs, logic '0' gives a normal (logic) output on these pins).

The sensitivity of each channel is set by correct selection of external components around each channel input

amplifier. See Section 5.4 and Figure 5 for a method of selecting amplifier gain and components to meet a

particular sensitivity requirement.

©2001 MX-COM, INC.

www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054

Doc. # 20480228.001

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

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