74VHC175 データシートの表示（PDF） - ON Semiconductor

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74VHC175

Quad D-Type Flip-Flop

ON Semiconductor 

Logic Symbol

IEEE/IEC

Logic Diagram

Functional Description

The VHC175 consists of four edge-triggered D flip-flops

with individual D inputs and Q and Q outputs. The Clock

and Master Reset are common. The four flip-flops will

store the state of their individual D inputs on the LOW-to-

HIGH clock (CP) transition, causing individual Q and Q

outputs to follow. A LOW input on the Master Reset (MR)

will force all Q outputs LOW and Q outputs HIGH inde-

pendent of Clock or Data inputs. The VHC175 is useful

for general logic applications where a common Master

Reset and Clock are acceptable.

Truth Table

Inputs @ tn,

MR = H

Dn

L

H

Outputs @ tn+1

Qn

Qn

L

H

H

L

H = HIGH Voltage Level

L = LOW Voltage Level

tn = Bit Time before Clock Pulse

tn+1 = Bit Time after Clock Pulse

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

©1993 Fairchild Semiconductor Corporation

74VHC175 Rev. 1.2

2

www.fairchildsemi.com

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