74VHC175 データシートの表示（PDF） - ON Semiconductor
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74VHC175 Datasheet PDF : 11 Pages
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AC Electrical Characteristics
Symbol
fMAX
Parameter
Maximum Clock
Frequency
tPLH, tPHL Propagation Delay Time,
(CP to Qn or Qn)
tPLH, tPHL Propagation Delay Time,
(MR to Qn or Qn)
tOSLH, tOSHL Output to Output Skew
CIN
Input Capacitance
CPD
Power Dissipation
Capacitance
VCC (V)
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
Conditions
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 50pF
CL = 50pF(3)
VCC = Open
(4)
TA = 25°C
Min. Typ. Max.
90 140
50 75
150 210
85 115
7.5 11.5
10.0 15.0
4.8 7.3
6.3 9.3
6.3 10.1
8.8 13.6
4.3 6.4
5.8 8.4
1.5
1.0
4
10
44
TA = –40°C
to +85°C
Min. Max.
75
45
125
75
1.0 13.5
1.0 17.0
1.0 8.5
1.0 10.5
1.0 12.0
1.0 15.5
1.0 7.5
1.0 9.5
1.5
1.0
10
Units
MHz
MHz
ns
ns
ns
ns
pF
pF
Notes:
3. Parameter guaranteed by design. tOSLH = |tPLHmax – tPLHmin|; tOSHL =| tPHLmax – tPHLmin|.
4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained from the equation:
ICC (opr.) = CPD • VCC • fIN + ICC/4 (per F/F), and the total CPD when n pcs of the Flip-Flop operate can be calculated
by the following equation: CPD (total) = 30 + 14 • n
AC Operating Requirements
Symbol
Parameter
tW(L), tW(H) Minimum Pulse Width (CP)
tW(L) Minimum Pulse Width (MR)
tS
Minimum Setup Time (Dn to CP)
tH
Minimum Hold Time (Dn to CP)
tREC
Minimum Removal Time (MR)
Note:
5. VCC is 3.3 ± 0.3V or 5.0 ± 0.5V
VCC (V)(5)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
TA = 25°C TA = –40°C to +85°C
Typ.
Guaranteed Minimum
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
4.0
4.0
1.0
1.0
1.0
1.0
5.0
5.0
5.0
5.0
Units
ns
ns
ns
ns
ns
©1993 Fairchild Semiconductor Corporation
74VHC175 Rev. 1.2
5
www.fairchildsemi.com
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