ML9213 データシートの表示（PDF） - LAPIS Semiconductor Co., Ltd.

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ML9213

56-Bit Duplex/Triplex (1/2 duty/1/3 duty) VFD Controller/Driver with Anode Digital Dimming

LAPIS Semiconductor Co., Ltd. 

1Semiconductor

FEDL9213-01

ML9213

FUNCTIONAL DESCRIPTION

Power-on Reset

When power is turned on, the ML9213 is initialized by the internal power-on reset circuit.

The status of the internal circuit after initialization is as follows:

N The contents of the shift registers and latches are set to “0”.

N The anode dimming duty cycle is set to “0”.

N All segment outputs (SEG1 to 56) are set to Low level.

N The GRID1 output is set to Low level.

N The GRID2 and GRID3 outputs are set to High level.

Data Transfer Method

Data can be transferred between the rising edge and the next falling edge of chip select input.

The mode data, segment data and anode dimming data are written by a serial transfer method. The serial data is

input to the shift register at the rising edge of a shift clock pulse.

The mode data (M0 to M2) must be transferred after the segment data and anode dimming data succeedingly.

When the chip select input falls, an internal LOAD signal is automatically generated and data is loaded to the

latches.

Set the shift clock to a High level except during data transfer.

CS

CLOCK

DATA IN

M0 M1 M2

Segment data or dimming data

Mode data

Function Mode

Function mode is selected by the mode data (M0 to M2). The relation between function mode and mode data is as

follows:

FUNCTION MODE

0

1

2

3

4

OPERATING MODE

Segment Data for GRID1-3 Input

Segment Data for GRID1 Input

Segment Data for GRID2 Input

Segment Data for GRID3 Input

Digital Dimming Data Input

MODE DATA

M0

M1

M2

0

0

0

1

0

0

0

1

0

1

1

0

0

0

1

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