SY88933ALKI(2005) データシートの表示（PDF） - Micrel

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SY88933ALKI
(Rev.:2005)

3.3V, 1.25Gbps PECL High-Sensitivity Limiting Post Amplifier w/TTL Signal Detect

Micrel 

Micrel, Inc

Functional Block Diagram

SY88933AL

Detailed Description

The SY88933AL low-power limiting post amplifier

operates from a single +3.3V power supply, over

temperatures from –40oC to +85oC. Signals with data

rates up to 1.25Gbps, and as small as 5mVpp, can be

amplified. Figure 1 shows the allowed input voltage

swing. The SY88933AL generates an SD output. SDLVL

sets the sensitivity of the input amplifier section.

Input Amplifier/Buffer

Figure 2 shows a simplified schematic of the

SY88933AL’s input stage. The high-sensitivity of the

input amplifier allows signals as small as 5mVpp to be

detected and amplified. The input amplifier also allows

input signals as large as 1800mVpp. Input signals are

linearly amplified with a typical 42dB differential voltage

gain. Since it is a limiting amplifier, the SY88933AL

outputs typically 1500mVpp voltage-limited waveforms

for input signals that are greater than 12mVpp.

Applications requiring the SY88933AL to operate with

high-gain should have the upstream TIA placed as close

as possible to the SY88933AL’s input pins to ensure the

best performance of the device.

Output Buffer

The SY88933AL’s PECL output buffer is designed to

drive 50Ω lines. The output buffer requires appropriate

termination for proper operation. An external 50Ω

resistor to VCC–2V for each output pin provides this.

Figure 3 shows a simplified schematic of the output

stage.

Signal-Detect

The SY88933AL generates a chatter-free SD open-

collector TTL output with an internal 4.75kΩ pull-up

resistor as shown in Figure 4. SD is used to determine

that the input amplitude is large enough to be

considered a valid input. SD asserts high if the input

amplitude rises above the threshold set by SDLVL and

de-asserts low otherwise. SD can be fed back to the

enable (EN) input to maintain output stability under a

loss of signal condition. EN de-asserts the true output

signal without removing the input signals. Typically,

3.4dB SD hysteresis is provided to prevent chattering.

Signal-Detect Level Set

A programmable SD level set pin (SDLVL) sets the

threshold of the input amplitude detection. Connecting

an external resistor between VCC and SDLVL sets the

voltage at SDLVL. This voltage ranges from VCC to VREF.

The external resistor creates a voltage divider between

VCC and VREF, as shown in Figure 5.

Hysteresis

The SY88933AL provides typically 3.4dB SD electrical

hysteresis. By definition, a power ratio measured in dB

is 10log (power ratio). Power is calculated as V2IN/R for

an electrical signal. Hence, the same ratio can be stated

as 20log (voltage ratio). While in linear mode, the

electrical voltage input changes linearly with the optical

power and hence, the ratios change linearly. Therefore,

the optical hysteresis in dB is half the electrical

hysteresis in dB given in the data sheet. The

SY88933AL is an electrical device, and this data sheet

refers to hysteresis in electrical terms. With 3.4dB SD

hysteresis, a voltage factor of 1.5 is required to assert or

de-assert SD.

May 2005

7

M9999-051205

hbwhelp@micrel.com or (408) 955-1690

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