84329AM-01 データシートの表示（PDF） - Integrated Device Technology
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84329AM-01
Integrated Device Technology
84329AM-01 Datasheet PDF : 20 Pages
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ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
nP_LOAD
X
L
M
X
Data
Inputs
N S_LOAD
X
X
Data
X
↑
Data Data
L
H
X
X
L
H
X
X
↑
H
X
X
↓
H
X
X
L
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
S_CLOCK
X
X
X
↑
L
L
X
S_DATA
X
X
X
Data
Data
Data
X
Conditions
Reset. M and N bits are all set HIGH.
Data on M and N inputs passed directly to M divider and
N output divider. TEST mode 000.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider
and N output divider.
M divide and N output divide values are latched.
Parallel or serial input do not affect shift registers.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
VCO Frequency
(MHz)
M Divider
256
M8
128
M7
64
M6
32
M5
16
M4
8
M3
4
M2
2
M1
1
M0
200
200
0
1
1
0
0
1
0
0
0
201
201
0
1
1
0
0
1
0
0
1
202
202
0
1
1
0
0
1
0
1
0
203
203
0
1
1
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
509
509
1
1
1
1
1
1
1
0
1
510
510
1
1
1
1
1
1
1
1
0
511
511
1
1
1
1
1
1
1
1
1
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
N1
N0
0
0
0
1
1
0
1
1
N Divider Value
1
2
4
8
Output Frequency (MHz)
Minimum Maximum
200
700
100
350
50
175
25
87.5
84329AM-01
www.idt.com
4
REV. D AUGUST 7, 2010
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