IRF6633APbF
+
-
RG
D.U.T
+
-
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
- +
• di/dt controlled by RG
• Driver same type as D.U.T.
VDD
+
• ISD controlled by Duty Factor "D"
-
• D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
* VGS=10V
D.U.T. ISD Waveform
Reverse
Recovery
Body Diode Forward
Current
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD
Re-Applied
Voltage
Body Diode
Inductoorr CCuurrernetnt
Forward Drop
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 18. Diode Reverse Recovery Test Circuit for N-Channel
HEXFET® Power MOSFETs
DirectFET Substrate and PCB Layout, MU Outline
(Medium Size Can, U-Designation).
Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations
D
S
G
S
D
G = GATE
D = DRAIN
S = SOURCE
D
D
Note: For the most current drawing please refer to IR website at http://www.irf.com/package
www.irf.com
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