ST14C02 データシートの表示（PDF） - STMicroelectronics
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ST14C02 Datasheet PDF : 12 Pages
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Table 3. Endurance and Data Retention
Device
Endurance (Erase/Write Cycles)
ST14C02C
1,000,000
ST14C02C
Data Retention (Years)
10
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to synchronize all data
in and out of the memory. A pull up resistor can be
connected from the SCL line to VCC. (Figure 4 in-
dicates how the value of the pull-up resistor can be
calculated).
Serial Data (SDA)
The SDA pin is bi-directional, and is used to trans-
fer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to VCC. (Figure 4 indicates how the value of the
pull-up resistor can be calculated).
Mode (MODE)
The MODE input may be driven dynamically. It
must be held at:
s VIL or VIH for the Byte Write mode
s VIH for Multibyte Write mode
s VIL for Page Write mode
When unconnected, the MODE input is internally
read as a VIH (Multibyte Write mode). Note that the
voltages are CMOS levels, and are not TTL com-
patible.
On the D15 micromodule, the MODE pin is not
connected to a contact. This pin is left floating on
the silicon. This type of ST14C02C is always in its
MultiByte mode, and cannot be changed from this.
DEVICE OPERATION
The memory device supports the I2C protocol, as
summarized in Figure 5. Any device that sends
data on to the bus is defined to be a transmitter,
and any device that reads the data to be a receiv-
er. The device that controls the data transfer is
known as the master, and the other as the slave.
A data transfer can only be initiated by the master,
which will also provide the serial clock for synchro-
nization. The memory device is always a slave de-
vice in all communication.
Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
20
VCC
16
12
8
4
VCC = 5V
SDA
MASTER SCL
RL
RL
CBUS
CBUS
0
100
200
300
400
CBUS (pF)
AI01100
3/12
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