DS2196 データシートの表示（PDF） - Maxim Integrated

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コンポーネント説明

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DS2196

T1 Dual Framer LIU

Maxim Integrated 

PIN

SYMBOL

43 TCLKOB

44 DVSS

45 DVDD

46 TCLKOA

47 TNEGOA /

TFSYNCA

48 TPOSOA /

TNRZA

49 TSERA

50 TCLKA

51 TSYNCA

52 TCHCLKA /

TLCLKA

53 TCHBLKA /

TLINKA

54 MUX

55 D0 / AD0

56 D1 / AD1

57 D2 / AD2

58 D3 / AD3

59 D4 / AD4

60 D5 / AD5

61 D6 / AD6

62 D7 / AD7

63 DVSS

64 DVDD

65 A0

66 A1

67 A2

68 A3

69 A4

70 A5

71 A6

72 A7 / ALE(AS)

73 RD*(DS*)

74 CS*

75 WR*(R/W*)

76 RCHBLKA /

RLINKA

77 RCHCLKA /

RLCLKA

78 RCLKIA

79 RPOSIA

80 RNEGIA

81 RCLKA

82 RSERA

83 RMSYNCA

84 RFSYNCA

85 RLOSA/

LOTCA

DS2196

TYPE

O

–

–

O

O

O

I

I

I/O

O

I/O

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

–

–

I

I

I

I

I

I

I

I

I

I

I

O

O

I

I

I

O

O

O

O

O

FUNCTION

Transmit Clock Output from Formatter B.

Digital Signal Ground.

Digital Positive Supply. 3.3V (±5%).

Transmit Clock Output from Formatter A.

Transmit Negative Data Output from Formatter A /

Transmit Frame Sync Pulse Output from Formatter A.

Transmit Positive Data Output / Transmit NRZ Data Output from

Formatter A.

Transmit Serial Data Input for Formatter A.

Transmit Clock Input for Formatter A.

Transmit Frame & Multiframe Pulse for/from Formatter A.

Transmit DS0 Channel Clock Output from Formatter A /

Transmit FDL Link Clock Output from Formatter A.

Transmit Channel Blocking Clock Output from Formatter A /

Transmit FDL Link Data Input for Formatter A.

Bus Operation. 0 = Non-Mux Bus / 1 = Mux Bus Operation.

Data Bus Bit 0 / Address/Data Bus Bit 0. LSB.

Data Bus Bit 1 / Address/Data Bus Bit 1.

Data Bus Bit 2 / Address/Data Bus Bit 2.

Data Bus Bit 3 / Address/Data Bus Bit 3.

Data Bus Bit 4 / Address/Data Bus Bit 4.

Data Bus Bit 5 / Address/Data Bus Bit 5.

Data Bus Bit 6 / Address/Data Bus Bit 6.

Data Bus Bit 7 / Address/Data Bus Bit 7. MSB.

I/O Digital Signal Ground.

I/O Digital Positive Supply. 3.3V (±5%).

Address Bus Bit 0. LSB.

Address Bus Bit 1

Address Bus Bit 2

Address Bus Bit 3

Address Bus Bit 4

Address Bus Bit 5

Address Bus Bit 6

Address Bus Bit 7 / Address Latch Enable (Address Strobe). MSB.

Read Input (Data Strobe).

Chip Select. Active Low Signal.

Write Input (Read/Write).

Receive Channel Blocking Clock Output from Framer A /

Receive FDL Link Data Output from Framer A.

Receive DS0 Channel Clock Output from Framer A /

Receive FDL Link Clock Output from Framer A.

Receive Clock Input for Framer A.

Receive Positive & NRZ Data Input for Framer A.

Receive Negative & NRZ Data Input for Framer A.

Receive Clock Output from Framer A.

Receive Serial Data Output from Framer A.

Receive Multiframe Pulse from Framer A.

Receive Frame Pulse from Framer A.

Receive Loss Of Synchronization from Framer A /

Loss of Transmit Clock Framer A.

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