DS21Q44 データシートの表示（PDF） - Maxim Integrated

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DS21Q44

Enhanced Quad E1 Framer

Maxim Integrated 

DS21Q44

device fully meets all of the latest E1 specifications including CCITT/ITU G.704, G.706, G.962, and

I.431 as well as ETS 300 011 and ETS 300 233.

1. INTRODUCTION

The DS21Q44 is a superset version of the popular DS21Q43 quad E1 framer offering the new features

listed below. All of the original features of the DS21Q43 have been retained and software created for the

original device is transferable to the DS21Q44.

NEW FEATURES

§ Additional hardware signaling capability including:

– receive signaling reinsertion to a backplane multiframe sync

– availability of signaling in a separate PCM data stream

– signaling freezing

– interrupt generated on change of signaling data

§ Per–channel code insertion in both transmit and receive paths

§ Full HDLC controller with 64-byte buffers in both transmit and receive paths. Configurable for Sa

bits or DS0 access

§ RCL, RLOS, RRA, and RUA1 alarms now interrupt on change of state

§ 8.192MHz clock synthesizer

§ Ability to monitor one DS0 channel in both the transmit and receive paths

§ Option to extend carrier loss criteria to a 1 ms period as per ETS 300 233

§ Automatic RAI generation to ETS 300 011 specifications

§ IEEE 1149.1 support

FUNCTIONAL DESCRIPTION

The receive side in each framer locates FAS frame and CRC and CAS multiframe boundaries as well as

detects incoming alarms including, carrier loss, loss of synchronization, AIS and Remote Alarm. If

needed, the receive side elastic store can be enabled in order to absorb the phase and frequency

differences between the recovered E1 data stream and an asynchronous backplane clock which is

provided at the RSYSCLK input. The clock applied at the RSYSCLK input can be either a 2.048 MHz

clock or a 1.544 MHz clock. The RSYSCLK can be a burst clock with speeds up to 8.192 MHz.

The transmit side in each framer is totally independent from the receive side in both the clock

requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic

store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for

E1 transmission.

READER’S NOTE:

This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125 us

frame, there are 32 8–bit timeslots numbered 0 to 31. Timeslot 0 is transmitted first and received first.

These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is

identical to channel 1, timeslot 1 is identical to Channel 2, and so on. Each timeslot (or channel) is made

up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is

the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used:

FAS

Frame Alignment Signal

CAS

Channel Associated Signaling

MF

Multiframe

Si

International bits

CRC4

CCS

Sa

E-bit

Cyclical Redundancy Check

Common Channel Signaling

Additional bits

CRC4 Error Bits

2 of 105

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