12028IBZ データシートの表示（PDF） - Renesas Electronics
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12028IBZ Datasheet PDF : 29 Pages
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ISL12028, ISL12028A
Serial Interface (I2C) Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
tAA
tBUF
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tHD:STO
tDH
Cb
PARAMETER
CONDITIONS
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of VDD,
until SDA exits the 30% to 70% of VDD
window.
Time the bus must be free before
the start of a new transmission
SDA crossing 70% of VDD during a
STOP condition, to SDA crossing 70%
of VDD during the following START
condition.
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
STOP Condition Hold Time for
Read, or Volatile Only Write
Output Data Hold Time
Capacitive Loading of SDA or SCL
Measured at the 30% of VDD crossing.
Measured at the 70% of VDD crossing.
SCL rising edge to SDA falling edge.
Both crossing 70% of VDD.
From SDA falling edge crossing 30%
of VDD to SCL falling edge crossing
70% of VDD.
From SDA exiting the 30% to 70% of
VDD window, to SCL rising edge
crossing 30% of VDD
From SCL falling edge crossing 70%
of VDD to SDA entering the 30% to
70% of VDD window.
From SCL rising edge crossing 70% of
VDD, to SDA rising edge crossing 30%
of VDD.
From SDA rising edge to SCL falling
edge. Both crossing 70% of VDD.
From SCL falling edge crossing 30%
of VDD, until SDA enters the 30% to
70% of VDD window.
Total on-chip and off-chip
MIN
(Note 16)
1300
1300
600
600
600
100
0
600
600
0
10
MAX
TYP (Note 16) UNITS NOTES
900
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
400
pF
Cpin
tWC
tR
tF
Cb
SDA, and SCL Pin Capacitance
Non-volatile Write Cycle Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
From 30% to 70% of VDD
From 70% to 30% of VDD
Total on-chip and off-chip
10
12
20
20 + 0.1 x Cb
250
20 + 0.1 x Cb
250
10
400
pF
ms
14
ns
15
ns
15
pF
15
RPU SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF.
1
Off-chip
For Cb = 400pF, max is about
2k~2.5k.
For Cb = 40pF, max is about
15k~20k
k
15
NOTES:
7. IRQ/FOUT Inactive (no frequency output and no alarms).
8. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz.
9. VRESET = 2.63V (VDD must be greater than VRESET), VBAT = 0V.
10. Bit BSW = 0 (Standard Mode), ATR = 00h, VBAT 1.8V.
11. Specified at +25°C.
12. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
13. Parameter is not 100% tested.
14. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
15. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
16. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN8233 Rev 10.00
August 14, 2015
Page 6 of 29
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